Hybrid-Bonded IC Assembly for Low-Parasitic Decoupling
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Solution Overview
Problem
As transistor sizes decrease and densities increase, finding area on integrated circuits (ICs) for decoupling capacitors becomes challenging, leading to increased parasitic inductance and capacitance along conductive paths, which affects power delivery and switching speeds.
Innovation Solution
The integration of reconstituted assemblies bonded together via hybrid bonding, with at least one passive component, such as a capacitive element, embedded in a reconstituted assembly, reduces the length of conductive elements between the passive component and semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are placed on the substrate to provide local charge reservoir, then power supply stability is improved, but substrate area consumption increases significantly
Solution Approach 1:
The patent moves decoupling capacitors from the substrate plane to the vertical dimension by placing them on separate capacitor dies that are stacked above the substrate using 3D integration techniques. This dimensional transition allows capacitors to be positioned close to the IC without consuming substrate area, resolving the contradiction between power supply stability and area utilization.
Solution Approach 2:
The patent embeds capacitor dies within the vertical stack of the IC package, nesting the capacitor component inside the package structure rather than placing it on the substrate surface. This nesting approach allows the capacitor to be in close proximity to the IC for effective decoupling while maintaining clean substrate area for other circuit elements.
2Speed
If transistor density is increased to improve performance, then processing speed is improved, but area available for decoupling capacitors decreases
Solution Approach 1:
By transitioning capacitor placement from 2D substrate mounting to 3D vertical stacking, the patent enables high transistor density on the substrate while maintaining adequate decoupling capacitance through vertically integrated capacitor dies, thus supporting both high processing speed and sufficient capacitor area.
3Ease of manufacture
If conventional bonding methods are used to attach components, then manufacturing simplicity is maintained, but conductive path length increases leading to higher parasitic effects
Solution Approach 1:
The patent segments the IC package into multiple stacked layers (substrate, capacitor dies, IC die) connected through vertical conductive vias. This segmentation enables direct vertical connections between capacitor terminals and IC power pins, dramatically reducing conductive path length and parasitic effects while maintaining manufacturability through standardized stacking processes.
Solution Approach 2:
The patent introduces intermediary conductive vias and bonding layers that facilitate direct electrical connection between the capacitor dies and IC power pins. These intermediaries create optimized current paths that minimize parasitic inductance and capacitance while maintaining ease of manufacture through established via and bonding techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic effects, such as inductance and capacitance, along conductive paths, thereby improving power delivery and reducing delays in transient responses at semiconductor dies.
Implementation Method 1
an integrated circuit assembly having reconstituted assemblies bonded together via hybrid bonding
Data Source
AI summary
Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.