Hybrid Bonded 3D IC Package Reducing I/O Pad Density
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Solution Overview
Problem
As semiconductor technologies advance, integrated circuit dies become smaller with increased functions, leading to a higher density of input/output (I/O) pads, which complicates die packaging and requires innovative solutions for enhanced parallel processing capabilities.
Innovation Solution
The integration of a memory device between two processor devices, such as a graphics processing unit and a central processing unit, using hybrid bonding to reduce the number of data signal lines in the redistribution structure, allowing for direct connections between semiconductor devices and enabling a more efficient packaging configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated circuit dies are made smaller with increased functions, then the number of I/O pads needed increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of I/O pads on the die surface to a three-dimensional stacked configuration using fan-out wafer-level packaging. Multiple dies are vertically stacked and interconnected through through-silicon vias and redistribution layers, effectively utilizing the vertical dimension to increase I/O capacity without requiring additional lateral area.
Solution Approach 2:
The patent implements a nested structure where multiple functional layers are stacked vertically within the package. Each die is nested within a larger package structure that includes redistribution layers, interconnect structures, and encapsulation materials. This nested arrangement allows multiple I/O pads to be accessed through a reduced footprint by distributing them across multiple vertical layers.
2Productivity
If multiple dies are integrated to increase parallel processing capabilities, then processing power increases, but packaging complexity increases
Solution Approach 1:
The patent divides the integrated circuit system into discrete functional segments or dies that can be independently manufactured and tested. Each die contains specific processing units or functional blocks, and these segmented dies are then stacked and interconnected using standardized interfaces and redistribution layers, making the complex multi-die system manageable through modular segmentation.
Solution Approach 2:
The patent employs universal interconnect structures and redistribution layers that can accommodate multiple different die types and configurations. The fan-out wafer-level packaging platform provides standardized mechanical, electrical, and thermal interfaces that work across various die implementations, reducing packaging complexity by using multi-functional interconnect structures that serve multiple purposes simultaneously.
3Quantity of substance
If I/O pad density is increased, then more functions can be integrated, but die packaging difficulty increases
Solution Approach 1:
The patent introduces redistribution layers and interconnect structures as intermediary elements between the high-density I/O pads on the die and the external package contacts. These intermediary layers buffer the complexity of high-density pad arrangements by providing additional routing flexibility, signal redistribution, and mechanical compliance, thereby facilitating easier packaging despite increased I/O density.
Data Source
AI summary
In an embodiment, a structure includes: a graphics processor device; a passive device coupled to the graphics processor device, the passive device being directly face-to-face bonded to the graphics processor device; a shared memory device coupled to the graphics processor device, the shared memory device being directly face-to-face bonded to the graphics processor device; a central processor device coupled to the shared memory device, the central processor device being directly back-to-back bonded to the shared memory device, the central processor device and the graphics processor device each having active devices of a smaller technology node than the shared memory device; and a redistribution structure coupled to the central processor device, the shared memory device, the passive device, and the graphics processor device.