Hybrid Bonded Image Sensor Architecture for High Sensitivity
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in maximizing photodiode area due to the need for transistor and circuitry space, which limits sensitivity as cameras become smaller and require higher pixel counts.
Innovation Solution
A hybrid bonded image sensor architecture where a photodiode die is separately fabricated and bonded with a supporting circuitry die, allowing for a higher percentage of surface area to be dedicated to photodiodes, with a differential amplifier system replacing traditional source followers for high-gain amplification and noise suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS image sensor architecture is used with transistors and circuitry integrated with photodiodes, then circuit functionality is achieved, but photodiode area is reduced limiting sensitivity
Solution Approach 1:
The image sensor is divided into two separate dies: a photodiode die containing only photodiodes and a supporting circuitry die containing all transistors and circuitry. This segmentation allows each die to be optimized independently, maximizing photodiode area on the photodiode die while maintaining full circuit functionality on the supporting circuitry die, thereby resolving the contradiction between sensitivity and area utilization.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture where the photodiode die and supporting circuitry die are bonded together vertically. This dimensional change allows simultaneous maximization of photodiode area on the first die and circuit density on the second die, eliminating the area trade-off present in conventional two-dimensional integration.
2Reliability
If photodiode area is increased to improve sensitivity, then image quality improves, but device size must be increased
Solution Approach 1:
By stacking the photodiode die and supporting circuitry die vertically through hybrid bonding, the patent achieves three-dimensional integration that maximizes photodiode area within a compact footprint. This vertical arrangement allows large photodiode arrays to be achieved without proportionally increasing the horizontal device dimensions, thus improving sensitivity while maintaining compact sensor volume suitable for smaller devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient use of space for photodiodes, optimizing their performance while allowing for compact sensor designs with high system conversion gain and effective analog signal processing, enhancing image sensitivity and pixel count in smaller devices.
Implementation Method 1
CMOS rectangular-array photosensor arrays are commonly used as image sensors in cameras. These arrays have an array of N by M photodiode-based photosensors
Implementation Method 2
Each supercell has a differential amplifier configurable to receive a noninverting input from a photodiode and an inverting input, the differential amplifier providing an output
Data Source
AI summary
A hybrid bonded image sensor has a photodiode die with macrocells having at least one photodiode and a bond contact; a supporting circuitry die with multiple supercells, each supercell having at least one macrocell unit bonded to the bond contact of a macrocell of the photodiode die. Each macrocell unit has a reset transistor adapted to reset photodiodes of the photodiode die macrocell. Each supercell has a differential amplifier configurable to receive a noninverting input from a photodiode and an inverting input, the differential amplifier providing an output, each differential amplifier has an amplifier reset transistor coupled to the differential amplifier output and the inverting input; a first capacitor coupled between the differential amplifier output and the inverting input, and a second capacitor coupled between the inverting input and a signal ground. The first and second capacitor of embodiments has controllable capacitance to adjust gain.