Hybrid-Bonded Memory Circuit for High Capacity and Low Latency
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Solution Overview
Problem
The manufacturing of high-capacity, low-latency memory circuits faces challenges due to the susceptibility of low-voltage logic circuits to thermal cycles, which degrades their performance and limits the thermal budget, and the complexity of integrating high-voltage and low-voltage circuits on the same chip, compromising scalability and cost-effectiveness.
Innovation Solution
The integration of quasi-volatile or non-volatile memory circuits on one semiconductor die and faster memory circuits on another, using hybrid bonding to decouple high-performance, low-voltage transistors from high-voltage and medium-voltage transistors, allowing advanced manufacturing nodes to optimize low-voltage circuit performance without exposing them to thermal cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage and low-voltage circuits are integrated on the same chip, then circuit functionality is improved, but manufacturing complexity and thermal management difficulty increase
Solution Approach 1:
The patent divides the memory circuit into separate high-voltage and low-voltage circuit regions on the same chip. High-voltage circuits (for memory array operations) are isolated from low-voltage circuits (for logic and control), allowing each to be optimized independently while maintaining overall functionality. This segmentation reduces manufacturing complexity by enabling separate process optimization.
Solution Approach 2:
The patent introduces intermediate voltage regulation circuits and isolation structures between high-voltage and low-voltage regions. These intermediary elements manage voltage transitions and prevent interference, enabling co-integration of different voltage circuits without compromising manufacturing yield or performance.
2Ease of manufacture
If low-voltage logic circuits are exposed to thermal cycles during manufacturing, then high-voltage memory circuits can be fabricated, but low-voltage circuit performance degrades
Solution Approach 1:
The patent employs preliminary protective measures during manufacturing by designing low-voltage logic circuits with thermal-resistant structures and selecting materials that withstand high-temperature processing. Threshold voltage compensation circuits are pre-configured to counteract thermal degradation effects, ensuring performance reliability after exposure to manufacturing thermal cycles.
Solution Approach 2:
The patent incorporates cushioning mechanisms such as voltage compensation circuits and thermal isolation structures that are built in advance to protect low-voltage circuits from thermal damage. These protective elements absorb thermal stress and prevent performance degradation before it occurs during subsequent operations.
3Quantity of substance
If memory capacity is increased, then storage capability is improved, but access latency increases
Solution Approach 1:
The patent transitions from planar memory architecture to three-dimensional vertical memory structures. By stacking memory arrays vertically and using through-silicon vias for interconnection, the design achieves higher storage capacity within the same footprint while maintaining short access paths. The vertical architecture enables high capacity without proportionally increasing access latency.
Solution Approach 2:
The patent divides the large-capacity memory into multiple smaller banks or segments that can be accessed independently. This segmentation allows parallel access operations and reduces the average access latency by enabling selective access to only the required memory portion rather than searching through the entire large capacity memory space.
Data Source
AI summary
A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.