Hybrid-Bonded Memory Stack for Thermal-Endurance Mismatch

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Solution Overview

Problem

Existing two-dimensional semiconductor devices face limitations in increasing integration density due to the need for high-resolution exposure equipment, which restricts the enhancement of semiconductor device performance and cost-effectiveness.

Innovation Solution

A stack type semiconductor device is developed, comprising hybrid-bonded first and second semiconductor structures with different thermal endurances, allowing for the integration of memory and control circuit layers formed at different substrates to maintain electrical reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high-resolution exposure equipment is used, then integration density is improved, but manufacturing cost increases

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by bonding memory and control circuit layers from separate substrates. This dimensional change enables higher integration density without requiring proportionally higher exposure resolution, as the stacking architecture achieves density through vertical arrangement rather than purely lateral miniaturization.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stack type semiconductor device achieves enhanced electrical reliability and improved thermal management by separating high-temperature memory layer formation from low-temperature control circuit layer formation, thereby reducing thermal burden and maintaining electrical characteristics.

Implementation Method 1

The second thermal endurance may be a thermal expansion temperature of the first bonding pads and the second bonding pads

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

The second bonding layer may be hybrid-bonded to the first bonding layer

Methodology Applied

Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20250133752A1Stack type semiconductor memory device

Publication Date: 2025.04.24 SK HYNIX INC

AI summary

A stack type semiconductor device includes a first semiconductor structure having a first integrated circuit layer and a first bonding layer and a second semiconductor structure having a second integrated circuit layer and a second bonding layer. The first integrated circuit layer has a first thermal endurance on one surface of the first integrated circuit layer. The first bonding layer is formed on the first integrated circuit layer. The second integrated circuit layer has a second thermal endurance, lower than the first thermal endurance, on one surface of the second integrated circuit layer. The second bonding layer is formed on the second integrated circuit layer and is hybrid-bonded to the first bonding layer. A third thermal endurance lower than the first thermal endurance. The third integrated circuit is arranged to face at least one of the first integrated circuit layer and the second integrated circuit layer.