Hybrid-Bonded Processor and Multi-Cache Stack for High-Bandwidth Routing
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Solution Overview
Problem
Existing two-dimensional scaling approaches for signal routing between processors and cache memory dies face physical limitations, hindering the development of high-performance semiconductor packages for advanced applications like artificial intelligence.
Innovation Solution
A three-dimensional stacking method using hybrid bonding to integrate a processor die with a combination of cache memories of different types, including SRAM, GCRAM, MRAM, and RRAM, through metal-to-metal bonding, creating a composite package with enhanced cache density and diverse design capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional scaling approaches are used for signal routing between processors and cache memory dies, then manufacturing simplicity is maintained, but signal bandwidth and signal delay performance deteriorate due to physical limitations
Solution Approach 1:
The patent transitions from two-dimensional planar routing to three-dimensional vertical stacking by bonding multiple dies together. The processor die is bonded to cache memory dies through metal-to-metal hybrid bonding, creating vertical signal paths that overcome the physical limitations of 2D scaling and enable higher signal bandwidth while reducing signal delay.
2Device complexity
If two-dimensional scaling approaches are used for signal routing, then device complexity is reduced, but signal delay increases due to physical limitations
Solution Approach 1:
The invention implements 3D stacking architecture where processor and cache memory dies are vertically bonded together. This creates direct short-distance vertical signal paths between processor cores and cache memories, dramatically reducing signal delay compared to long horizontal paths in 2D layouts, while the modular die-stack design keeps overall system complexity manageable.
3Productivity
If multiple levels of cache memories are integrated using hybrid bonding, then signal bandwidth is enhanced, but device complexity increases
Solution Approach 1:
The patent divides the memory hierarchy into multiple separate cache memory dies (e.g., L1 cache die, L2 cache die, L3 cache die) that are vertically stacked and bonded to the processor die. Each cache level is implemented as a distinct die with specialized functionality, allowing high-bandwidth parallel access while managing complexity through modular segmentation rather than monolithic integration.
Solution Approach 2:
Multiple cache levels are arranged in vertical layers above the processor die through hybrid bonding. This 3D configuration enables simultaneous access to multiple cache levels from different vertical positions, increasing signal bandwidth while the layered structure organizes complexity in a manageable spatial hierarchy.
4Quantity of substance
If cache density is enhanced through 3D stacking, then manufacturing precision requirements increase, but this enables high-performance processing applications
Solution Approach 1:
The patent combines metal-to-metal bonding with dielectric-to-dielectric bonding in a hybrid bonding approach. The metal layers provide electrical connections and mechanical bonding, while the dielectric layers provide structural support and alignment features. This combination distributes the precision requirements across multiple material systems rather than relying on a single bonding interface, enabling high cache density through 3D stacking while managing manufacturing precision challenges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high bandwidth signal paths and meets the demands of high-performance processing applications by integrating multiple cache levels, enhancing cache density and versatility for various design requirements.
Implementation Method 1
through metal-to-metal bonding
Data Source
AI summary
A device structure may be formed by bonding a processor die with at least one memory die using metal-to-metal bonding. The processor die comprises processing units for performing logical operations. The at least one memory die comprises at least two types of memory arrays selected from a static random access memory array, a gain cell random access memory array, and magnetoresistive random access memory array, and a resistive random access memory array. A bonded assembly of the processor die and the at least one memory die is formed. The bonded assembly can be bonded to an interposer using a first array of solder material portions that is bonded to on-die bump structures of the processor die and to a first subset of first bump structures of the interposer.