Hybrid-Bonded Package Structure With Integrated Passive Devices
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Solution Overview
Problem
Conventional semiconductor packaging methods require additional processes for integrating passive devices with interposers, leading to increased package size and reduced miniaturization potential, as well as compatibility issues between chip and substrate connections.
Innovation Solution
A package structure and method that integrates a passive device directly into the interposer or on its surface using a hybrid bonding process, eliminating the need for surface mount technology and allowing for precise matching of passive device parameters with chips, thereby reducing interposer area and enhancing power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive devices are connected to the interposer by surface mount technology, then the interposer can be electrically connected to the passive device, but the package size increases and the process compatibility is reduced
Solution Approach 1:
The patent merges the passive device layer with the interposer structure by forming the passive device layer on the same substrate as the interposer. This integration eliminates the need for separate surface mount technology processes and reduces the overall package area while maintaining electrical connection reliability.
Solution Approach 2:
The interposer substrate serves multiple functions simultaneously: it provides the interposer structure for chip mounting and also hosts the passive device layer. This multi-functionality reduces the number of separate components needed and improves process compatibility with flip chip bonding.
2Reliability
If passive devices are connected by surface mount technology, then electrical connection is achieved, but process compatibility with flip chip bonding is reduced
Solution Approach 1:
The patent combines the passive device formation process with the interposer fabrication process, allowing both to be manufactured using the same semiconductor fabrication techniques. This merging enables process compatibility with flip chip bonding while achieving reliable electrical connections.
3Area of stationary object
If passive devices are integrated directly into the interposer, then the package structure is miniaturized, but the passive device parameters may not match the chip requirements
Solution Approach 1:
The patent implements local quality by allowing different regions of the passive device layer to have different electrical characteristics. This enables precise matching of passive device parameters with chip requirements in specific locations while maintaining overall package miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves process compatibility, miniaturizes the package structure, and enhances power integrity by placing passive devices close to chips for local energy storage, achieving precise matching and improved performance in high-speed circuits.
Implementation Method 1
bonding the interposer to the device substrate by a hybrid bonding process using the first surface of the first redistribution layer and the first surface of the second redistribution layer as a bonding surface
Data Source
AI summary
A method for forming a package structure includes: providing an interposer, which includes a first redistribution layer including a first set of conductive pads and a second set of conductive pads; providing a device substrate, which includes a passive device layer and a second redistribution layer covering the passive device layer, the passive device layer including at least one passive device, and the second redistribution layer including a third set of conductive pads and a fourth set of conductive pads; bonding the interposer to the device substrate by a hybrid bonding process; removing part of the passive device layer from a surface, facing away from the interposer, of the device substrate; and arranging at least one chip on the surface, facing away from the interposer, of the device substrate, chip is electrically connected to the fourth set of conductive pads.