Hybrid-Bonded Semiconductor Package With Separated Signal and Power Routing
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Solution Overview
Problem
Current semiconductor packages face challenges in reducing the length of input/output (I/O) paths between logic chips, leading to increased path lengths and potential entanglement between signal and power distribution lines, which affects performance and reliability.
Innovation Solution
The semiconductor package employs hybrid bonding between semiconductor chips and a connection die, with power distribution wiring layers on the rear surfaces and signal lines on the front surfaces, minimizing the I/O path length and enhancing signal transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If signal lines and power distribution lines are routed on the same surface, then wiring is simplified, but line entanglement occurs and signal integrity deteriorates
Solution Approach 1:
The patent separates signal lines and power distribution lines into different spatial dimensions by routing signal lines on the front surface and power distribution lines on the rear surface of the semiconductor chip, eliminating entanglement while maintaining wiring simplicity
Solution Approach 2:
The patent divides the chip into functionally distinct regions: a front surface for signal processing and a rear surface for power distribution, allowing independent optimization of each function without interference
2Speed
If I/O path length is reduced, then signal transfer speed improves, but routing flexibility decreases
Solution Approach 1:
By utilizing the rear surface of the chip for power distribution, the patent creates additional routing space that allows short signal paths on the front surface while maintaining flexibility in power line routing through via connections
3Reliability
If hybrid bonding is used between chips, then connection reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent prepares bonding pads and via structures in advance during chip fabrication, enabling reliable hybrid bonding without requiring complex post-fabrication processing or alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the length of I/O paths, preventing entanglement and improving performance by allowing efficient signal transfer between logic chips, thereby increasing the reliability and efficiency of the semiconductor package.
Implementation Method 1
a hybrid bonding is established between the connection die and the first semiconductor chip and between the connection die and the second semiconductor chip
Data Source
AI summary
Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip, and a connection die. A hybrid bonding may be established between the connection die and the first semiconductor chip and between the connection die and the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having first and second surfaces. The first surface is closer than the second surface to the connection die. The second semiconductor chip includes a second semiconductor substrate having third and fourth surfaces. The third surface is closer than the fourth surface to the connection die. The first and second semiconductor chips further include a power distribution wiring layer on the second surface of the first semiconductor chip and the fourth surface of the second semiconductor substrate.