Hybrid-Bonded Semiconductor Package With Asymmetric Pad Alignment Margin
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Solution Overview
Problem
In the hybrid bonding process of semiconductor packages, accurately aligning the bonding surfaces of multiple semiconductor chips or substrates is crucial to ensure reliable connections, but existing methods lack sufficient alignment margins as the pitch between bonding pads narrows.
Innovation Solution
The solution involves designing semiconductor packages where the connection pads of upper and lower semiconductor chips differ in size, providing an alignment margin during hybrid bonding. Specifically, the connection pads and insulation layers are arranged such that the pads directly contact each other, and the insulation layers directly contact, with the pads being larger in one direction and the insulation layers being wider in the opposite direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between bonding pads is narrowed to increase I/O density, then the quantity of connections increases, but the alignment precision required increases and manufacturing reliability deteriorates
Solution Approach 1:
The patent applies asymmetry by making the connection pads of the first semiconductor chip larger than those of the second semiconductor chip. This asymmetric design creates a unidirectional alignment margin that allows for positional deviations during bonding while maintaining reliable electrical connections, thus resolving the contradiction between high I/O density and alignment precision requirements
Solution Approach 2:
The patent implements beforehand cushioning by designing the larger connection pads to provide an alignment margin in advance. This margin acts as a buffer that compensates for potential misalignment during the bonding process, ensuring connection reliability even when pitch is narrowed for higher I/O density
2Reliability
If the connection pads are made larger to provide alignment margin, then the alignment reliability improves, but the area occupied by pads increases reducing available bonding area
Solution Approach 1:
The asymmetric pad design allows one chip to have larger pads while the other has smaller pads, optimizing the balance between alignment margin and bonding area. The larger pads on one side provide the necessary alignment tolerance, while the smaller pads on the other side minimize area consumption, thus resolving the contradiction between bonding reliability and available bonding area
Solution Approach 2:
The patent applies local quality by differentiating the pad sizes between different chips and potentially different regions. This localized variation in pad dimensions allows alignment margins to be provided only where necessary, rather than uniformly increasing all pad sizes, thus maintaining optimal bonding area while ensuring bonding reliability
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip including a first semiconductor layer, and a first connection pad and a first insulation layer that are provided on a surface of the first semiconductor layer extending in a first direction; and a second semiconductor chip including a second semiconductor layer, and a second connection pad and a second insulation layer that are provided on a surface of the second semiconductor layer. The first connection pad directly contacts the second connection pad and is provided on the second connection pad in a second direction that is perpendicular to the first direction. The first insulation layer directly contacts the second insulation layer, the first insulation layer is provided on the second insulation layer in the second direction. A width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.