3D Hybrid-Bonded RF Circuit Layout for Lower Parasitics
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Solution Overview
Problem
Reducing die size in radio frequency (RF) products leads to increased parasitic capacitance, resistance, and thermal management issues, affecting signal integrity and noise, while requiring more complex and costly manufacturing processes.
Innovation Solution
A method of fabricating RF circuits using three-dimensional, hybrid wafer-level bonded wafers with complementary metal-oxide semiconductor (CMOS) processing, involving the bonding of silicon-on-insulator (SOI) wafers to create stacked transistors in a folded configuration, reducing layout size and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If die size is reduced to improve device size and processing speed, then smaller devices and faster processing are achieved, but parasitic capacitance and resistance increase, affecting signal integrity and frequency response
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by bonding multiple SOI wafers together. This dimensional change allows circuit components to be arranged in the vertical dimension (stacked transistors across multiple wafers) rather than being constrained to a single plane, thereby reducing the horizontal layout area while maintaining signal integrity through shorter interconnect paths between stacked components.
2Area of moving object
If die size is reduced to achieve smaller devices, then device footprint is reduced, but thermal management becomes less effective due to reduced heat dissipation area
Solution Approach 1:
The patent utilizes the vertical dimension through multi-wafer stacking to reduce the horizontal footprint of the device. Heat dissipation is improved by conducting heat vertically through the stacked wafer structure to larger heat sink areas on the outer surfaces of the top and bottom wafers, effectively managing thermal loads in a compact footprint by exploiting the third dimension for both circuit integration and thermal management.
3Productivity
If die size is reduced to improve integration density, then more components fit in smaller area, but manufacturing process control becomes more complex and costly
Solution Approach 1:
The patent divides the integrated circuit into multiple separate SOI wafers that are processed independently using standard CMOS techniques. Each wafer can be manufactured using conventional processes with established control methodologies, avoiding the need for single-wafer ultra-fine-pitch processing. The wafers are then bonded together to achieve high integration density, thereby segmenting the manufacturing complexity while maintaining high productivity.
4Area of moving object
If wafer-level hybrid bonding is used to reduce layout size, then smaller RF circuit layouts are achieved, but bonding process precision requirements increase
Solution Approach 1:
The patent performs preliminary actions during the individual wafer fabrication process by forming alignment marks, bonding pads, and interconnect structures before the bonding step. The SOI wafers are processed with precise patterning and metallization layers that prepare the bonding interfaces in advance. This preliminary preparation enables the subsequent wafer-level hybrid bonding to achieve precise alignment and low-resistance connections without requiring excessively tight bonding process tolerances.
Data Source
AI summary
The present disclosure provides a method of fabricating radio frequency (RF) circuits using three-dimensional (3D), hybrid wafer-level bonded wafers. In one aspect, a first, bottom silicon-on-insulator (SOI) wafer and a second, top SOI wafer are provided. Complementary metal-oxide semiconductor processing is then performed on both the first and second SOI wafers to fabricate transistors and form RF circuits on each wafer. The second wafer is then bonded to the first wafer to electrically couple the RF circuits together. In an aspect, the 3D fabrication method enables RF circuits that are designed using transistor structures stacked in a three-dimensional (3D) folded configuration using a plurality of wafers. In one aspect, the RF circuit uses mirrored portions that are folded together during the wafer bonding process. In another aspect, the RF circuit uses asymmetric portions between the top versus bottom wafers.