Hybrid Bonded Stacked Interconnect Layout for Circuit Redesign
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Solution Overview
Problem
Existing multi-stacked electronic devices face challenges in changing metal line layouts for circuit redesign due to face-to-face interconnection difficulties and reticle field layout arrangement issues, particularly in wafer-on-wafer bonding.
Innovation Solution
The implementation of a hybrid bonding technique with metal-to-metal and dielectric-to-dielectric bonding regions, along with flexible face-to-face interconnections, allows for easier reticle field layout adjustments by eliminating the need for precise alignment of circuit layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If face-to-face interconnection is used for multi-stacked devices, then shorter interconnections and lower resistance are achieved, but circuit redesign becomes difficult due to fixed metal line layout
Solution Approach 1:
The patent divides the interconnection structure into multiple segments: through-silicon vias (TSVs) for vertical connections, copper blocks for intermediate connections, and metal lines on different levels. This segmentation allows independent modification of each segment, enabling circuit redesign while maintaining the face-to-face interconnection architecture.
Solution Approach 2:
The patent introduces flexible metal lines and adjustable via positions that can be reconfigured for different circuit designs. The metal line layout is not fixed but can be dynamically adjusted in different embodiments to accommodate new circuit requirements while maintaining electrical performance.
2Productivity
If wafer-on-wafer bonding is used for multi-stacked devices, then device integration is achieved, but reticle field layout arrangement becomes complex and difficult to adjust
Solution Approach 1:
The patent moves the interconnection design from a two-dimensional planar layout to a three-dimensional vertical-stack architecture. By utilizing vertical TSVs and multi-level metal lines, the design decouples the reticle field layout constraints, allowing independent optimization of each wafer layer without complex 2D arrangement constraints.
Solution Approach 2:
The patent establishes a modular interconnection framework with standardized TSV and copper block structures that can be pre-configured. This preliminary structure provides a flexible foundation that simplifies subsequent reticle field layout arrangements, as the basic interconnection architecture is already in place and can be adapted to different circuit designs.
3Reliability
If precise alignment is required for circuit layers in wafer-on-wafer bonding, then bonding reliability is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent introduces copper blocks and via structures as intermediary elements between circuit layers. These intermediaries provide alignment references and tolerance compensation, reducing the precision requirements for direct wafer-to-wafer alignment while maintaining bonding reliability through standardized interface structures.
Data Source
AI summary
An electronic device and a method for manufacturing the same are provided. The electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. The first metal layer electrically connects the upper electronic structure to the upper connection structure. The second metal layer electrically connects the lower electronic structure to the lower connection structure. The upper connection structure and the lower connection structure are bonded together.