Hybrid Bonding of CMOS and Memory Wafers With Debondable Carriers

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Solution Overview

Problem

Semiconductor wafer debonding processes, particularly in temporary bonding applications, face challenges such as thermal stress, warping, cracking, and breakage due to varying material expansion coefficients and strong bonding interfaces, which impact manufacturing yield and device reliability, especially when stacking memory array wafers with CMOS wafers.

Innovation Solution

A hybrid bonding scheme using a debondable carrier wafer with a 'dielectric layer-debond layer-dielectric layer' stack structure, allowing for mechanical or chemical-assisted debonding, and incorporating inert ions or metallic layers to facilitate cleaving, ensuring minimal damage to the semiconductor wafers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If strong bonding interface is used to join semiconductor wafers, then bonding strength is improved, but debonding difficulty increases causing wafer damage

Engineering Contradiction:

Improvebonding strengthVSAvoidwafer integrity during debonding

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The bonding interface is segmented into two distinct layers: a strong covalent bond layer formed directly between semiconductor wafers for strong bonding, and a separate sacrificial debond layer deposited on the carrier wafer that enables controlled debonding. This segmentation allows the bonding strength and debonding ease to be independently optimized.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A sacrificial debond layer (intermediary layer) is introduced between the carrier wafer and the semiconductor wafer. This intermediary layer acts as a mediator that absorbs the stress during debonding and provides a controlled failure plane, preventing direct stress transmission to the semiconductor wafer that would cause damage.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If thermal processing is used for wafer bonding, then bonding quality is improved, but thermal stress causing warping and cracking increases

Engineering Contradiction:

Improvebonding qualityVSAvoidthermal stress

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The bonding process parameters are changed from high-temperature thermal bonding to low-temperature hybrid bonding. The covalent bond layer forms at temperatures below 200°C, significantly reducing thermal stress and preventing warping and cracking while maintaining bonding quality.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

A composite bonding structure is used consisting of a covalent bond layer (such as silicon oxide or silicon nitride) combined with a sacrificial debond layer. This composite structure enables bonding at lower temperatures while providing controlled debonding capability, avoiding the thermal stress problems of traditional high-temperature bonding.

Inventive Principle:

Principle #40Composite materials

3Stability of the object's composition

If carrier wafer is used for temporary bonding support, then handling stability is improved, but debonding complexity increases

Engineering Contradiction:

Improvehandling stabilityVSAvoiddebonding process complexity

Core Design Contradiction:

Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The sacrificial debond layer is deposited on the carrier wafer before bonding the semiconductor wafer. This preliminary action prepares a pre-defined debonding interface in advance, so that when debonding is needed, it can be simply initiated without complex processes. The layer is already in position to provide controlled failure.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The sacrificial debond layer is designed as a disposable, consumable component that is intentionally made to fail during debonding. It is a low-cost material layer that serves its purpose temporarily during the bonding process and then is sacrificed to enable simple wafer separation, reducing overall process complexity.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient separation of bonded wafers without causing damage, maintaining wafer integrity and functionality, and allowing reuse or recycling of carrier wafers, thus improving manufacturing yield and reducing costs.

Implementation Method 1

incorporating inert ions or metallic layers to facilitate cleaving, ensuring minimal damage to the semiconductor wafers

Methodology Applied

Scientific EffectCleavage: Fracture Mechanics

Data Source

PatentUS20260011682A1Hybrid bonding of semiconductor CMOS wafer and semiconductor memory array wafer using debondable carriers

Publication Date: 2026.01.08 MICRON TECHNOLOGY INC

AI summary

The present technology relates to hybrid bonding of semiconductor memory wafer and semiconductor CMOS wafer using one or more debondable carriers. In one embodiment, a semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor wafer having complementary metal-oxide-semiconductor (CMOS) transistor devices, the first semiconductor wafer having a first frontside surface and a first backside surface, and a second semiconductor wafer having one or more memory arrays, the second semiconductor wafer having a second frontside surface and a second backside surface, wherein a bonding interface is formed between the first backside surface of the first semiconductor wafer and the second frontside surface of the second semiconductor wafer, and wherein the first semiconductor wafer has a first dielectric layer disposed on its first frontside surface.