Hybrid Bonding Layer Planarity Without Diffusion Barriers
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Solution Overview
Problem
Existing semiconductor manufacturing processes, such as dual damascene metallization techniques, are limited by the need for diffusion barriers and complex planarization methods, which complicate fabrication and are not compatible with all wafer sizes, particularly 200 mm wafers.
Innovation Solution
A new manufacturing method for hybrid bonding layers that eliminates the use of diffusion barriers and employs a novel chemical mechanical polishing (CMP) process to achieve an enhanced planarity of hybrid bonding pads, allowing for efficient bonding without the need for dual damascene metallization techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual damascene metallization techniques are used with copper, then electrical connection is achieved, but diffusion barriers are required which complicate the fabrication process
Solution Approach 1:
The patent extracts and removes the diffusion barrier layer from the metallization structure. By using tungsten instead of copper, the need for diffusion barriers is eliminated entirely, simplifying the fabrication process while maintaining reliable electrical connections through the tungsten conductor and dielectric interface
Solution Approach 2:
The patent changes the material parameter from copper to tungsten, which fundamentally alters the requirements for the metallization structure. Tungsten's inherent resistance to diffusion into dielectric materials eliminates the need for additional barrier layers, thereby reducing fabrication complexity while preserving electrical functionality
2Manufacturing precision
If chemical mechanical polishing with ceria slurry is used, then planarized bonding surface is achieved, but significant contamination is introduced requiring additional cleaning steps
Solution Approach 1:
The patent changes the CMP slurry composition parameter from ceria-based to a ceria-free formulation. This modification maintains the planarization function while eliminating the source of contamination, thereby achieving both surface precision and reduced harmful factors without requiring additional cleaning steps
Solution Approach 2:
The patent converts the potentially harmful effect of CMP slurry contamination into a benefit by developing a ceria-free slurry formulation. The modified slurry maintains effective planarization capabilities while inherently preventing contamination, turning a previously harmful process into a clean manufacturing step
3Reliability
If dual damascene process is used, then copper interconnect is achieved, but the process is not compatible with 200 mm wafer CMOS fabrication processes with non-copper BEOL metallization
Solution Approach 1:
The patent creates a universal metallization approach using tungsten that can be applied across different wafer sizes (200 mm and 300 mm) and CMOS fabrication processes regardless of the underlying BEOL metallization material. The tungsten-based dual damascene structure provides interconnect functionality compatible with aluminum, copper, or other non-copper BEOL layers, achieving broad adaptability while maintaining reliable electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables hybrid bonding in 200 mm wafer fabrication processes without the limitations of dual damascene techniques, resulting in a simplified manufacturing process with improved planarity and reduced contamination, facilitating efficient and cost-effective semiconductor device production.
Implementation Method 1
a novel chemical mechanical polishing (CMP) process to achieve an enhanced planarity of hybrid bonding pads
Implementation Method 2
a conductor comprising a conductor material covering at least part of the surface
Data Source
AI summary
A semiconductor device comprises a substrate body with a surface, a conductor comprising a conductor material covering at least part of the surface, and a dielectric that is arranged on a part of the surface that is not covered by the conductor. Therein, the conductor is in contact with the substrate body, the conductor and the dielectric form a layer, and a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body. Moreover, the semiconductor device is free of a diffusion barrier.