Hybrid Bonding of Stacked Memory Dies With Debris-Resistant Surfaces
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Solution Overview
Problem
Manufacturing processes for stacked semiconductor systems often result in debris accumulation on die surfaces, which adversely affects electrical connections and leads to device rejection, while existing cleaning methods may cause damage or fail to adequately remove particles.
Innovation Solution
Implementing wafer reconstruction, planarization, and bonding operations such as W2W, C2W, and S2W bonding, along with dielectric material application, to form a reconstructed wafer and stack semiconductor devices, reducing particle collection and enhancing structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manufacturing processes are performed for stacked semiconductor systems, then semiconductor devices are produced, but debris accumulates on die surfaces affecting electrical connections
Solution Approach 1:
The patent applies preliminary action by performing cleaning operations and applying dielectric materials to die surfaces before bonding occurs. This prevents debris from interfering with electrical connections during the bonding process, thereby maintaining productivity while eliminating the harmful effect of debris accumulation.
Solution Approach 2:
The patent introduces dielectric material as an intermediary layer between die surfaces. This dielectric layer acts as a mediator that protects electrical connections from debris while still allowing for proper bonding, thus resolving the contradiction between maintaining production efficiency and preventing debris-related defects.
2Object-affected harmful factors
If cleaning methods are applied to remove particles, then debris is reduced, but die surfaces may be damaged or cleaning may be insufficient
Solution Approach 1:
The patent changes the parameters of the cleaning process by controlling the aggressiveness and duration of cleaning operations. By optimizing these parameters, the patent achieves effective particle removal while maintaining die surface integrity, thus resolving the contradiction between cleaning effectiveness and surface damage prevention.
Solution Approach 2:
The patent uses dielectric material as an intermediary protective layer that is applied after cleaning. This layer protects the cleaned surface from re-contamination and provides a reliable bonding surface, ensuring both particle removal and surface integrity are maintained.
3Reliability
If debris is present on die surfaces, then electrical connections are adversely affected, but increasing cleaning intensity may cause damage
Solution Approach 1:
The patent performs preliminary cleaning and dielectric material application before bonding to ensure electrical connection quality. By addressing the debris issue beforehand with a controlled, multi-step process, the patent maintains reliable electrical connections without requiring excessively complex or aggressive cleaning operations.
Solution Approach 2:
The dielectric material serves as an intermediary that protects electrical connections from debris. This allows for a balanced approach where moderate cleaning is performed followed by dielectric application, achieving reliable electrical connections without the need for overly complex cleaning processes.
4Strength
If wafer reconstruction and bonding operations are implemented, then structural integrity is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct operations: wafer reconstruction, planarization, cleaning, dielectric material application, and bonding. By dividing the complex manufacturing process into manageable segments, the patent achieves enhanced structural integrity while keeping each individual step relatively simple and well-controlled.
Solution Approach 2:
The patent performs preliminary wafer reconstruction and planarization operations before bonding to ensure structural integrity. By preparing the wafers in advance with proper surface preparation and alignment, the actual bonding operation becomes simpler and more reliable, thus achieving strong structural integrity without excessively complex bonding procedures.
Data Source
AI summary
Methods, systems, and devices for hybrid bonding techniques for stacked semiconductor systems are described. A semiconductor device may be formed to include a stack of memory array dies. Each memory array die of the stack may be bonded with at least one other memory array die in the stack. The semiconductor device may include a set of multiple dielectric material portions, with each dielectric material portion extending beyond a lateral boundary of the stack and extending from a respective semiconductor substrate portion of a corresponding memory array die. The semiconductor device may also include a logic die bonded with a first memory array die of the stack, and the logic die may include circuitry operable to facilitate one or more access operations of the memory array dies of the stack.