Hybrid Bonding Pad Ratios for Reliable Semiconductor Packages

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Solution Overview

Problem

In semiconductor packaging, the bonding of chips and substrates with fine pitch using hybrid bonding techniques faces issues of delamination and cracking due to thermal expansion of bonding pads, leading to reliability concerns.

Innovation Solution

The semiconductor package design includes specific ratios for the width and thickness of connection pads between chips to minimize stress during thermal expansion, with a width ratio of the second connection pad to the first connection pad ranging from 0.5 to 1.1 and a thickness ratio ranging from 1.6 to 2.1, ensuring optimal adhesion and reducing the likelihood of delamination or cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If hybrid bonding is used to achieve fine pitch bonding, then bonding precision is improved, but reliability deteriorates due to delamination and cracking from thermal expansion

Engineering Contradiction:
Improvebonding precisionVSAvoidjunction reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by optimizing the width ratio and thickness ratio of connection pads. Specifically, the width ratio of the upper connection pad to the lower connection pad is controlled within 0.5-1.1, and the thickness ratio is controlled within 1.6-2.1. These parameter adjustments balance the thermal expansion characteristics of the bonding interface, reducing stress concentration while maintaining fine pitch bonding capability, thus resolving the contradiction between bonding precision and junction reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements local quality by creating asymmetric connection pad structures where the upper and lower pads have different width and thickness dimensions. The upper connection pad is designed with specific width and thickness ratios relative to the lower pad, creating localized structural optimization at the bonding interface. This local structural differentiation allows differential thermal expansion accommodation at the critical bonding zone while maintaining overall fine pitch bonding precision

Inventive Principle:
Principle #3Local quality

2Area of moving object

If connection pad dimensions are reduced for fine pitch, then area is reduced, but stress concentration increases leading to delamination and cracking

Engineering Contradiction:
Improveconnection pad areaVSAvoidstress concentration
Core Design Contradiction:
Area of moving objectVSStress or pressure

Solution Approach 1:

The patent employs asymmetry by designing the upper and lower connection pads with different dimensional proportions. The width ratio (0.5-1.1) and thickness ratio (1.6-2.1) create an asymmetric structure where the upper pad has optimized dimensions relative to the lower pad. This asymmetric design allows the connection pads to distribute thermal stress more effectively during bonding, preventing stress concentration that would lead to delamination and cracking while maintaining reduced area for fine pitch applications

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the reliability of the junction by controlling stress on the connection pads, thereby improving the bonding process and reducing the occurrence of delamination or cracking, ensuring stable chip-to-chip connections.

Implementation Method 1

as bonding pads are exposed to high temperatures and thermally expand, the pads may be delaminated or cracks may occur at the interface

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250022824A1Semiconductor package and method for fabricating the same
Publication Date: 2025.01.16 SAMSUNG ELECTRONICS CO LTD
  • US20250022824A1 patent drawing
  • US20250022824A1 patent drawing
  • US20250022824A1 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip including a first semiconductor layer including a surface which extends in a first direction; and a first connection pad provided on the surface of the first semiconductor; and a second semiconductor chip including a second semiconductor layer; and a second connection pad provided on a surface of the second semiconductor layer. The first connection pad is directly connected to the second connection pad and a ratio of a width of the second connection pad in the first direction to a width of the first connection pad in the first direction is less than or equal to 1.1 and greater than or equal to 0.5.