Hybrid Bonding Probe Pad Layout for TSV Package Testing
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Solution Overview
Problem
Current advancements in System on Integrated Chips (SoIC) technology face challenges with hybrid bonding, particularly at the interface between back-side bond pad metal (BSBPM) and bond pad metal (BPM), leading to inadequate bonding strength and circuit probe test failures due to poor contact, affecting performance and reliability.
Innovation Solution
A monitoring circuit layout is introduced for hybrid bonding wafer acceptance testing (WAT) design, focusing on chip boundaries and scribe line areas, incorporating circuit probe pads, bond pads, metal lines, and daisy chain structures to assess bonding quality, enabling early detection of bonding issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid bonding is performed at the interface between back-side bond pad metal and bond pad metal, then device integration is achieved, but bonding strength is insufficient leading to poor contact
Solution Approach 1:
The patent applies preliminary action by performing wafer acceptance testing (WAT) before final bonding operations. Monitoring circuits are formed and tested in advance to identify bonding quality issues early in the manufacturing process, allowing corrective actions to be taken before committing to irreversible bonding steps, thereby improving bonding strength and contact quality
Solution Approach 2:
The patent implements feedback mechanisms through monitoring circuits that provide real-time information about bonding interface quality. The WAT process uses test results from these monitoring circuits to feedback on bonding conditions, enabling process adjustment and optimization to achieve reliable bonding strength and contact quality
2Reliability
If monitoring circuit layout is implemented for wafer acceptance testing, then bonding quality can be assessed early, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the monitoring function into separate, dedicated monitoring circuits that are distinct from the main device circuits. These monitoring circuits are specifically designed for WAT purposes and can be independently formed and tested, allowing bonding quality assessment without significantly complicating the main manufacturing process
Solution Approach 2:
The monitoring circuits serve multiple functions: they act as both test structures for WAT and can potentially serve as functional elements in the final device. This multi-functionality reduces the need for separate dedicated test structures, thereby limiting the increase in manufacturing process complexity while still enabling early bonding quality assessment
Data Source
AI summary
A method includes bonding a first semiconductor die to a first substrate, the semiconductor die comprising a second substrate and a through-substrate via (TSV) extending at least partially through the second substrate; forming a first dielectric material laterally surrounding the first semiconductor die; forming a probe pad over the first dielectric material; forming a bond pad over the TSV, the bond pad being electrically coupled to the probe pad; bonding a second semiconductor die to the first semiconductor die through the bond pad, wherein the probe pad is laterally offset from the second semiconductor die.