Hybrid Bonding Process Flow for Smaller-Pitch Substrate-to-Die Interconnects
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Solution Overview
Problem
As semiconductor package sizes shrink and complexity increases, existing interconnect methods face challenges in maintaining signal integrity and reliability with smaller bump pitches, particularly in applications where top die chiplets are expensive, and traditional methods like top die first processes are undesirable.
Innovation Solution
The use of hybrid bonding techniques that combine embedded metal, such as copper, with dielectric materials like silicon oxide to form interconnections between substrates and silicon dies, allowing for efficient and effective use of smaller bump pitches while maintaining solder joint integrity through copper-copper direct bonding surrounded by dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If pitch bump scaling is used to shrink package size, then package size is reduced, but signal integrity and reliability deteriorate
Solution Approach 1:
The patent changes the bonding parameters by using direct copper-to-copper bonding at lower temperatures (below 200°C) compared to traditional solder bump processes. This parameter change enables smaller bump pitches while maintaining signal integrity and reliability through direct metal bonding without solder joint degradation.
Solution Approach 2:
The patent employs composite bonding structures combining copper metal layers with dielectric materials. The copper-copper direct bond is surrounded and protected by dielectric material, creating a composite interconnect structure that maintains signal integrity at reduced pitch dimensions while providing mechanical support and electrical isolation.
2Ease of manufacture
If traditional top die first processes are used, then assembly is simplified, but cost increases for expensive top die chiplets
Solution Approach 1:
The patent inverts the traditional assembly sequence by performing copper-copper direct bonding first, then adding the dielectric material afterward. This inverted process flow eliminates the need for expensive top die first processes, reduces assembly complexity, and lowers overall manufacturing cost while maintaining reliability.
3Quantity of substance
If smaller bump pitches are used, then interconnection density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces traditional mechanical solder bump formation and alignment processes with direct copper-copper bonding at the atomic level. This substitution eliminates the need for precise mechanical alignment of solder bumps, enabling smaller pitch dimensions with relaxed manufacturing precision requirements through self-aligning direct metal bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and efficient electrical connections with smaller bump pitches, maintaining signal integrity and reducing assembly process complexity, suitable for advanced packaging architectures like multi-chip monolithic packaging.
Implementation Method 1
Hybrid bonding combines embedded metal (such as copper (Cu)) with dielectric bonds (such as silicon oxide (SiOx)), to form permanent bonds
Implementation Method 2
Hybrid bonding combines embedded metal (such as copper (Cu)) with dielectric bonds (such as silicon oxide (SiOx)), to form permanent bonds
Data Source
AI summary
Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.