Hybrid Bonding on Rectangular Substrate Panels for High-Density I/O
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Solution Overview
Problem
Traditional semiconductor manufacturing processes face challenges with low input/output (IO) density due to the need for redistribution layers and round silicon substrates, which increase manufacturing costs and parts count, and limit effective bonding area.
Innovation Solution
The use of hybrid bonding techniques to attach semiconductor chips directly to advanced rectangular substrate panels with high-density conductive connections, eliminating the need for interposers and underfill materials, and enabling high bandwidth communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional thermocompression bonding with RDLs is used, then electrical connections are established, but IO density is reduced due to additional space requirements for RDLs and fan-out connections
Solution Approach 1:
The patent extracts and eliminates the RDL layer from the traditional bonding structure. By using direct hybrid bonding between chip pads and substrate contacts, the intermediate RDL redistribution layer is removed, allowing pads to be placed directly over active devices without requiring additional routing space, thereby increasing IO density while maintaining connection reliability
Solution Approach 2:
The patent transitions from planar RDL-based connections to vertical through-substrate contacts. By forming contacts that extend through the substrate thickness dimension, electrical connections are established in the vertical dimension rather than requiring lateral RDL routing, enabling higher IO density without compromising connection reliability
2Ease of manufacture
If round silicon substrates are used, then chip bonding is enabled, but effective substrate area is reduced limiting rectangular chip utilization
Solution Approach 1:
The patent replaces the traditional round silicon substrate with an asymmetric rectangular substrate geometry. This asymmetric shape better matches the rectangular form factor of modern chips, maximizing the effective bonding area and improving space utilization while maintaining all necessary chip bonding capabilities
Solution Approach 2:
The rectangular substrate serves multiple functions: it provides the bonding surface for chips, enables higher IO density through direct hybrid bonding, and optimizes space utilization for rectangular chip packages. This multi-functional design eliminates the need for separate interposer structures
3Reliability
If RDLs and fan-out connections are formed, then electrical connections are established, but manufacturing cost and parts count increase
Solution Approach 1:
The patent merges the substrate and interconnection functions into a single integrated structure. By forming contacts directly through the substrate and bonding them directly to chip pads, the separate RDL layer and its associated manufacturing processes are eliminated, reducing parts count and manufacturing complexity while maintaining electrical connection capability
Solution Approach 2:
The patent extracts and removes the RDL intermediate layer from the connection path. Direct hybrid bonding between chip pads and substrate contacts eliminates the need for RDL formation, reflow soldering, and underfill processes, thereby reducing manufacturing steps, parts count, and overall cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases IO density, reduces manufacturing costs and parts count, and enhances electrical performance by minimizing interface materials and interconnect lengths, while allowing for more efficient use of substrate area and flexible chip-to-substrate integration.
Implementation Method 1
bonding the first top surface of the first semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections
Implementation Method 2
chemical mechanical polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of approximately 0.5 nm or less prior to performing the hybrid bonding process
Data Source
AI summary
Methods for bonding semiconductor surfaces leverage hybrid bonding processes to enable heterogeneous integration architectures. In some embodiments, the methods may comprise forming a semiconductor structure on a silicon-based substrate with a first set of exposed conductive connections on a top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than approximately 10 microns. Forming an advanced rectangular substrate panel with a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than approximately 10 microns. Bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process to bond the semiconductor structure to the advanced rectangular substrate panel.