Hybrid Bonding Structure for 3D Die Stacks With Test Pad Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable and efficient 3D packaging and 3DICs due to issues with electrical shorts and leakage currents, particularly in the bonding process of stacked dies, which affect the integration density and performance of electronic components.
Innovation Solution
The solution involves forming a hybrid bonding structure with a blocking layer and dummy metal layers to electrically isolate test pads, preventing electrical shorts and enhancing the reliability of the die stack structure by using a combination of metal-to-metal and non-metal-to-non-metal bonding, along with a redistribution circuit structure and encapsulation to facilitate efficient interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked over chips to form 3DICs, then integration density and bandwidth are improved, but electrical shorts and leakage currents occur in the bonding process
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the first and second chips during bonding. This dielectric layer acts as an insulating barrier that prevents direct electrical contact between conductive elements of adjacent chips, thereby eliminating electrical shorts and leakage currents while allowing the chips to remain bonded together in a stacked configuration.
Solution Approach 2:
The bonding interface between chips is segmented into distinct functional zones: a first bonding region for electrical connection and a second bonding region for mechanical support. This segmentation allows selective application of bonding materials and processes in different areas, enabling reliable electrical connections while preventing unwanted electrical contact through strategic placement of dielectric materials in non-bonding areas.
2Productivity
If smaller feature sizes are used, then more components can be integrated into a given area, but manufacturing precision requirements increase
Solution Approach 1:
Conductive elements are formed on the first chip before the second chip is bonded to it. This preliminary formation of conductive structures allows for precise patterning and positioning to be accomplished during the initial chip fabrication process, rather than requiring equally precise operations during the subsequent bonding process. The pre-formed conductive elements serve as templates that guide the bonding alignment and material deposition.
3Reliability
If hybrid bonding structure with blocking layer is used, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The dielectric layer and blocking structures are applied selectively only in specific regions where electrical isolation is needed, rather than uniformly across the entire chip surface. The first and second bonding regions are differentiated in function and material composition, with dielectric materials placed only where required to prevent electrical shorts. This localized application of complex structures maintains simplicity in areas where basic bonding suffices.
Data Source
AI summary
A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure.