Hybrid Bonding Via Layout for 3DIC Wafer Alignment
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Solution Overview
Problem
The challenge of wafer distortion due to asymmetric bonding wave paths caused by unbalanced layouts in three-dimensional integrated circuits (3DICs) during the bonding of semiconductor dies, leading to misalignment and poor circuit performance.
Innovation Solution
The implementation of a redistribution layer with a hybrid bonding technique that balances bonding wave propagation paths by adjusting the layout of conductive contacts to ensure symmetric wave propagation, using a combination of metal-to-metal and dielectric-to-dielectric bonds, and employing an integrated circuit manufacturing system to modify the layout for improved symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If asymmetric layouts of bonding layers are used in 3DICs, then functional density and integration density can be increased, but wafer distortion occurs due to unbalance bonding wave paths
Solution Approach 1:
The patent applies asymmetry principle by intentionally introducing dummy bonding layers to compensate for the inherent asymmetry in the functional bonding layer layout. The dummy bonding layers are strategically placed to balance the bonding wave propagation paths, transforming the asymmetric structure into a balanced configuration that prevents wafer distortion while maintaining high integration density
2Adaptability or versatility
If asymmetric bonding layer layouts are used, then circuit functionality can be optimized, but alignment accuracy deteriorates due to unbalance bonding wave paths
Solution Approach 1:
The patent resolves this contradiction by using dummy bonding layers to create symmetric bonding wave propagation paths, thereby maintaining high alignment accuracy while preserving the asymmetric functional layout needed for circuit performance
3Ease of manufacture
If conventional bonding techniques are used without layout modification, then manufacturing process is simple, but wafer distortion and misalignment occur
Solution Approach 1:
The patent applies preliminary action by modifying the bonding layer layout design before the actual bonding process. Dummy bonding layers are incorporated into the design stage to pre-compensate for potential wafer distortion, allowing conventional bonding techniques to proceed without complex modifications while achieving high precision results
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wafer distortion and enhances alignment accuracy, minimizing misalignment issues and improving the performance and scalability of 3DICs by ensuring consistent bonding wave velocity across different directions.
Implementation Method 1
a bonding wave is used to bond the first integrated circuit component to the second integrated circuit component
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, and a redistribution layer over the interconnect structure. The redistribution layer includes bonding vias arranged in a plurality of arrays with rows each extending along a first direction and columns each extending along a second direction. Across the redistribution layer, a ratio of a total number of the columns of the arrays along the first direction over a total number of the rows of the arrays along the second direction ranges from about 0.5 to about 1.5.