Hybrid Boost Circuit Design for Faster Memory Writes with Lower Die Area
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Solution Overview
Problem
Existing memory technologies face inefficiencies in write operation speed and power consumption due to the struggle between NMOS and PMOS transistors during data node discharge, leading to increased memory footprint and manufacturing costs.
Innovation Solution
Implementing a hybrid boost circuit that combines a boost transistor with a metal line capacitor to provide scalable negative voltage boosting, reducing the size of the boost transistor and minimizing excessive capacitance across varying memory sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large boost transistor is used to provide sufficient boost capacitance, then write operation speed is improved, but semiconductor die space is increased
Solution Approach 1:
The boost capacitance function is segmented between two components: a small boost transistor and a metal line capacitor. The metal line capacitor provides the majority of the boost capacitance through its physical structure (first metal line adjacent to second metal line), while the small boost transistor provides control functionality. This segmentation allows sufficient boost capacitance without requiring a large transistor area.
Solution Approach 2:
The invention transitions from relying solely on transistor dimensions to provide capacitance to utilizing the spatial arrangement of metal lines in a different dimensional space. The metal line capacitor uses adjacent metal lines extending along the bit line to provide capacitance, effectively using the bit line's length dimension to generate boost capacitance without increasing transistor area.
2Reliability
If traditional boost circuits are used, then write assist is provided, but excessive capacitance is created across varying memory sizes
Solution Approach 1:
The metal line capacitor's capacitance value dynamically adapts to memory size because it is formed by metal lines whose length and configuration scale with the bit line length. As memory size varies, the bit line length changes, and consequently the metal line capacitor provides proportionally appropriate capacitance, preventing excessive capacitance in smaller memories while maintaining sufficient capacitance in larger memories.
Solution Approach 2:
The metal line capacitor automatically provides the appropriate amount of boost capacitance based on its physical coupling to the bit line it serves. The capacitor structure inherently scales with the bit line dimensions, eliminating the need for external adjustment or sizing calculations, and naturally adapting to different memory configurations.
3Reliability
If larger boost transistors are used to ensure sufficient capacitance, then write operation reliability is improved, but manufacturing costs increase
Solution Approach 1:
The capacitance provision function is segmented from the transistor, allowing the use of a small, inexpensive transistor combined with a metal line capacitor. This segmentation reduces the need for large transistor fabrication while maintaining sufficient total capacitance, thereby lowering manufacturing complexity and cost.
Solution Approach 2:
The metal line capacitor serves multiple functions: it provides boost capacitance, utilizes existing metal line infrastructure, and scales automatically with memory size. This multi-functionality reduces the need for additional dedicated components, simplifying the manufacturing process and reducing overall production costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances write operation speed while conserving semiconductor die space and reducing power consumption by optimizing boost capacitance according to memory size, thus lowering manufacturing costs.
Implementation Method 1
a metal line capacitor including a first metal line and an at least one second metal line extending adjacent to the first metal line
Implementation Method 2
a boost transistor; and a metal line capacitor including a first metal line and an at least one second metal line extending adjacent to the first metal line, wherein the first metal line is coupled to the bit line and to a gate of the boost transistor
Data Source
AI summary
A memory is provided that includes a negative bit line hybrid boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The hybrid boost circuit uses a charged gate capacitance of a boost transistor and a charged capacitance of a metal line capacitor to provide the negative bit line boost. Similarly, the memory may include a word line hybrid boost circuit that uses another boost transistor and another metal line capacitor for boosting a word line above a word line power supply voltage during the write operation.