Hybrid SRAM-eDRAM Cache Layout for Area and Latency Balance

Solution Overview

Problem

The area and standby power challenges of large SRAM-based caches in System on a Chip (SoC) designs are addressed by integrating dynamic random-access memory (DRAM) and static random-access memory (SRAM) to enhance cache performance and efficiency.

Innovation Solution

The integration of eDRAM memory cells with TFT selector transistors in higher metal layers and memory peripheral circuits in lower layers, along with a hierarchical memory system that includes both SRAM and eDRAM, reduces footprint and improves latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a large SRAM-based cache is used to handle memory bandwidth, then cache capacity is improved, but area and standby power consumption increase significantly

Engineering Contradiction:

Improvecache capacityVSAvoidcache area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The cache is segmented into two distinct parts: an SRAM-based cache for frequently accessed data and an eDRAM-based cache for less frequently accessed data. This segmentation allows the system to achieve large total cache capacity while using area-efficient eDRAM for the majority of the cache, thereby reducing overall area consumption compared to a purely SRAM-based large cache.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different memory technologies are assigned to different functional regions: SRAM is used for the L1 cache where fast access is critical, while eDRAM is used for the L2 cache where capacity and area efficiency are more important. This local quality assignment optimizes the trade-off between speed and area for each specific cache level.

Inventive Principle:

Principle #3Local quality

2Quantity of substance

If a large SRAM-based cache is used to handle memory bandwidth, then cache capacity is improved, but standby power consumption increases significantly

Engineering Contradiction:

Improvecache capacityVSAvoidstandby power consumption

Core Design Contradiction:

Quantity of substanceVSUse of energy by stationary object

Solution Approach 1:

The cache is segmented into two distinct parts: an SRAM-based cache for frequently accessed data and an eDRAM-based cache for less frequently accessed data. This segmentation allows the system to achieve large total cache capacity while using area-efficient eDRAM for the majority of the cache, thereby reducing overall area consumption compared to a purely SRAM-based large cache.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different memory technologies are assigned to different functional regions: SRAM is used for the L1 cache where fast access is critical, while eDRAM is used for the L2 cache where capacity and area efficiency are more important. This local quality assignment optimizes the trade-off between speed and area for each specific cache level.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If eDRAM is used instead of SRAM for large cache, then area and standby power are improved, but access speed and latency increase

Engineering Contradiction:

Improvecache areaVSAvoidaccess latency

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The cache is segmented into two distinct parts: an SRAM-based cache for frequently accessed data and an eDRAM-based cache for less frequently accessed data. This segmentation allows the system to achieve large total cache capacity while using area-efficient eDRAM for the majority of the cache, thereby reducing overall area consumption compared to a purely SRAM-based large cache.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system implements a hierarchical cache structure where data is pre-loaded from eDRAM to SRAM when accessed frequently, and the memory controller predicts access patterns to pre-fetch data into the faster SRAM cache before it is needed, thereby reducing the perceived latency for frequently accessed data.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12572299B2Method and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM)

Publication Date: 2026.03.10 INTEL CORP

AI summary

Methods and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM). In one embodiment, the integrated circuit comprises a static random-access memory (SRAM) device to store a first portion of data of a processor, a dynamic random-access memory (DRAM) device to store a second portion of the data of the processor, and a memory control circuit to read from both the SRAM and DRAM devices, a first set of bits of a first word to be read from the SRAM device and a second set of bits of the first word to be read from the DRAM device.