Hybrid Hardware Software Cache Refill for Address Translation Jitter
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Solution Overview
Problem
Current processing systems face challenges in translating external memory addresses to internal memory addresses quickly enough to meet the high-speed demands of applications like streaming video and graphics, where both predictable and unpredictable data accesses require real-time responses, with existing hardware and software cache refill mechanisms being insufficient for achieving low jitter and fast processing speeds.
Innovation Solution
A combined hardware and software cache refill mechanism is implemented, where both mechanisms operate simultaneously to manage address translation table caches, with the software mechanism pre-loading cache lines before a cache miss and the hardware mechanism handling unpredictable data accesses, allowing for faster and more efficient data translation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If only hardware cache refill mechanism is used, then fast processing speed is achieved, but jitter cannot be sufficiently reduced for real-time applications
Solution Approach 1:
The patent combines hardware and software cache refill mechanisms into a unified system. The hardware mechanism (cache refill circuit) provides fast processing speed, while the software mechanism (cache refill function) pre-loads predictable data accesses to reduce jitter. Both mechanisms operate simultaneously on the same address translation table cache, merging their advantages to resolve the contradiction between speed and reliability.
Solution Approach 2:
The software cache refill function performs preliminary action by pre-loading cache lines before they are actually needed. This predictive pre-loading reduces the jitter associated with unpredictable data accesses, while the hardware mechanism continues to handle fast refills when needed, thus improving reliability without sacrificing speed.
2Reliability
If software cache refill mechanism is used, then jitter is reduced for predictable data accesses, but processing speed is insufficient for real-time requirements
Solution Approach 1:
The patent merges software and hardware cache refill mechanisms so that software handles predictable accesses (reducing jitter) while hardware handles unpredictable accesses (maintaining speed). Both mechanisms operate concurrently on the same cache, allowing the system to achieve low jitter for predictable patterns while maintaining fast processing for unpredictable patterns.
Solution Approach 2:
The system applies different cache refill strategies to different types of data accesses. Software pre-loading is applied to predictable data accesses (local optimization for jitter reduction), while hardware refilling is applied to unpredictable data accesses (local optimization for speed). This localized quality approach resolves the speed-reliability contradiction.
3Speed
If address translation is performed quickly to meet speed objectives, then real-time performance is improved, but cache management complexity increases
Solution Approach 1:
The address translation table cache serves multiple functions: it is refilled by hardware for fast unpredictable accesses and pre-loaded by software for predictable accesses. This multi-functionality allows the same cache structure to handle both speed-critical and jitter-critical operations, improving address translation speed without proportionally increasing complexity.
Solution Approach 2:
The patent merges hardware and software cache management into a coordinated system. The hardware cache refill circuit and software cache refill function work together on the same address translation table cache, sharing data structures and management logic. This merging approach improves translation speed while controlling complexity through unified cache management rather than separate systems.
Data Source
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AI summary
Methods and apparatus provide a hardware implemented cache refill circuit for managing at least one address translation table cache, the at least one address translation table cache containing data used to translate an external address into a physical address of a processing system; provide a software implemented cache refill function also for managing the at least one address translation table cache; and simultaneously refill the at least one address translation table cache using the hardware implemented cache refill circuit and the software implemented cache refill function.