Hybrid Cache and Scratch Pad Memory Architecture for Processor Data Access
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Solution Overview
Problem
Current processor architectures face inefficiencies in data access times due to the limitations of cache memory and Scratch Pad Memory (SPM) in handling load and store instructions, with cache memory having high complexity and high data latency in multi-port SPM configurations, which affects overall instruction processing speed.
Innovation Solution
A processor architecture that combines a single-port cache and a multi-port SPM, where load and store instructions are allocated based on analyzed characteristics, allowing for efficient data management by optimizing latency and processing speed through compiler-driven allocation and timestamp-based scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to store data accessed by the processor core, then data access speed is improved for frequently accessed data, but data access latency increases when data is not stored in the cache memory
Solution Approach 1:
The memory system is segmented into two distinct memory structures: cache memory for frequently accessed data and Scratch Pad Memory (SPM) for other data. This segmentation allows the system to optimize access patterns for different data types, reducing overall access latency by directing appropriate data to the appropriate memory structure.
Solution Approach 2:
The SPM acts as an intermediary memory structure between the cache and main memory. It handles data that doesn't fit the cache's LRU replacement pattern, preventing cache pollution and maintaining cache efficiency while providing fast access for non-cache data.
2Productivity
If multi-port SPM is used to handle multiple load/store operations, then instruction processing parallelism is improved, but data latency increases due to high complexity
Solution Approach 1:
The system dynamically allocates data between cache and SPM based on access patterns and instruction characteristics. The compiler analyzes load/store instructions and determines optimal memory placement, allowing the system to adapt to different workloads and optimize for either cache hits or SPM efficiency depending on the situation.
Solution Approach 2:
The system changes the operational parameters of different memory structures based on the type of data being accessed. Cache uses LRU replacement policy for temporal locality, while SPM uses direct mapping for spatial locality. This parameter differentiation optimizes performance for different access patterns without requiring a single complex unified structure.
3Reliability
If cache memory is used for all data access, then temporal locality is exploited effectively, but spatial locality and data throughput are limited
Solution Approach 1:
The memory system is segmented into two distinct memory structures: cache memory for frequently accessed data, and Scratch Pad Memory (SPM) for other data. This segmentation allows the system to optimize access patterns for different data types, reducing overall access latency by directing appropriate data to the appropriate memory structure.
Solution Approach 2:
The hybrid memory system provides universal support for different access patterns by combining cache and SPM. The cache handles temporal locality requirements while the SPM handles spatial locality and bulk data transfer requirements, making the system universally effective for various types of data access workloads.
Data Source
AI summary
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.