Hybrid Timing in Pipelined Cache Memories to Limit Bit-Line Discharge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional large cache memories waste power due to unnecessary discharge of bit lines during read and write cycles, which is exacerbated by densely arranging bit cells, leading to increased power consumption and performance issues in modern computing systems.
Innovation Solution
Implement a hybrid timing mode in cache memories using a self-timing clock signal that precedes the main clock signal to disable the word line earlier, reducing unnecessary power consumption without affecting data transmission timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line is enabled for the entire clock period to ensure complete data access, then data retrieval is reliable, but power consumption increases due to unnecessary discharge of bit lines
Solution Approach 1:
The patent applies preliminary action by introducing a self-timing clock signal that triggers earlier than the main clock signal to disable the word line. This preliminary disabling action occurs before the main clock's second rising edge, preventing unnecessary bit line discharge while ensuring data access completes within the reduced time window. The sense amplifier is enabled in advance to capture data before the word line is fully disabled, resolving the contradiction between reliability and energy loss.
2Loss of energy
If the clock period is reduced to shorten word line enable time and reduce power waste, then power consumption decreases, but processor instruction fetch and decode performance deteriorates
Solution Approach 1:
The patent segments the clock signal into two independent components: the main clock signal that governs processor operations and remains unchanged for maintaining performance, and a separate self-timing clock signal that controls cache memory operations. This segmentation allows the cache memory to operate with shorter effective access times (reducing power consumption) while the processor continues to run at the original, faster clock rate, thus resolving the contradiction between power savings and processor performance.
3Quantity of substance
If densely arranged bit cells are used to increase storage capacity, then cache memory capacity increases, but power consumption increases due to long bit columns and continuous discharge
Solution Approach 1:
The self-timing clock signal enables preliminary action by disabling the word line before the main clock's second rising edge. This early disabling prevents continuous discharge of long bit columns in densely packed cache memories, significantly reducing power consumption while preserving the high storage capacity enabled by dense bit cell arrangement. The sense amplifier's advance enablement ensures data is captured before discharge begins, maintaining reliability despite the shortened access window.
Data Source
AI summary
In various embodiments, a computer-implemented method for controlling cache memory accesses comprises transmitting a first clock signal to the cache memory, where a first rising edge of the first clock signal asserts a word line, and transmitting a second clock signal to the cache memory, where a first rising edge of the second clock signal precedes a second rising edge of the first clock signal, and the first rising edge of the second clock signal de-asserts the word line.