Hybrid Capacitor With Coplanar Electrodes For Leakage Reduction
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Solution Overview
Problem
In the miniaturization of semiconductor devices, existing capacitor structures face challenges such as incomplete filling of conductive materials and seam generation in pillar stacks, which affect the performance and reliability of capacitors.
Innovation Solution
The semiconductor device incorporates a hybrid structure with a first lower electrode having an insulating core and a second lower electrode with a cylindrical shape, both sharing coplanar outer side surfaces, along with supporter patterns and a capacitor dielectric layer that extends through the second lower electrode and into the first lower electrode, preventing exposure of contact plugs and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a pillar stack structure is used to miniaturize capacitors, then the effective surface area is increased, but conductive material may not be fully filled and seams may be generated
Solution Approach 1:
The patent employs a nested structure where a first lower electrode with pillar shape is placed inside a second lower electrode with cylindrical shape. This nested configuration allows the capacitor structure to achieve increased effective surface area while ensuring complete filling of conductive materials, as the outer cylindrical electrode provides a enclosing structure that prevents seam formation in the inner pillar electrode.
2Volume of moving object
If miniaturization is pursued to increase integration, then device size is reduced, but capacitor performance and reliability may deteriorate
Solution Approach 1:
The patent utilizes a composite capacitor structure combining two different electrode geometries (pillar-shaped and cylindrical) within a single capacitor unit. This composite approach enables miniaturization while maintaining reliability, as the dual-structure design provides both space efficiency for high integration and structural integrity for consistent performance, avoiding the reliability issues associated with single-structure miniaturization.
3Ease of manufacture
If coplanar outer side surfaces are configured for first and second lower electrodes, then manufacturing alignment is simplified, but structural complexity increases
Solution Approach 1:
The patent applies local quality by configuring only the outer side surfaces of the first and second lower electrodes to be coplanar, while allowing other portions of the electrodes to maintain their distinct pillar and cylindrical geometries. This selective coplanar configuration simplifies manufacturing alignment processes without requiring complete geometric simplification, thus achieving ease of manufacture while accepting localized structural complexity only where necessary.
Data Source
AI summary
A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.