Hybrid Clock Domain Crossing Verification for IC Design
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Solution Overview
Problem
Current clock domain crossing (CDC) verification processes in integrated circuit (IC) design are incomplete and error-prone, relying on unvalidated assumptions and leading to partial proof, which complicates the decision-making process for designers and does not ensure comprehensive coverage.
Innovation Solution
A hybrid CDC verification method and system that performs static and dynamic verification, generating assertions and monitors, and iteratively improves coverage through simulation, allowing for explicit assumption handling and comprehensive validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If functional analysis is performed to achieve comprehensive CDC verification, then verification accuracy is improved, but computation time and complexity increase significantly
Solution Approach 1:
The verification process is divided into three distinct phases: structural analysis (fast, incomplete), functional analysis (computation-intensive, comprehensive), and simulation-based validation (practical testing). This segmentation allows the system to perform quick structural checks first, then selectively apply more intensive functional analysis only when needed, reducing overall computation complexity while maintaining verification accuracy.
Solution Approach 2:
The patent employs partial functional analysis by using simulation results to validate CDC verification claims. Instead of requiring complete functional analysis for all cases, the system uses simulation to provide practical validation that may be sufficient for closing verification, especially when structural analysis shows no violations. This partial action approach reduces computation complexity while maintaining adequate verification accuracy for practical purposes.
2Reliability
If assumptions are made during CDC verification to improve analysis accuracy, then verification results become more reliable, but the verification process becomes less transparent and more error-prone
Solution Approach 1:
The system provides feedback by comparing structural analysis results with simulation results. When structural analysis indicates potential violations or when simulation reveals issues not caught by structural analysis, the system feeds back to require revisiting and resolving those issues. This feedback loop ensures that assumptions made during verification are validated against actual simulation behavior, improving reliability while maintaining transparency through traceable verification paths.
Solution Approach 2:
Simulation acts as an intermediary between structural analysis and final verification conclusions. Rather than directly making assumptions about functional behavior, the system uses simulation as an intermediate validation step that bridges structural analysis results with practical verification requirements. This intermediary approach allows assumptions to be tested against actual circuit behavior without directly embedding unvalidated assumptions into the verification logic.
3Productivity
If structural analysis is performed alone, then verification speed is improved, but verification completeness deteriorates due to incomplete analysis
Solution Approach 1:
The system performs structural analysis as a preliminary action that provides quick initial verification results. This fast structural analysis is then followed by targeted simulation-based validation to confirm critical findings. The preliminary structural analysis achieves high productivity for routine cases, while the subsequent simulation validation ensures completeness only when structural analysis indicates potential issues or when closure requirements demand higher assurance.
Data Source
AI summary
A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification.