Hybrid-Channel Nanosheet FET Stack for CMOS Channel Separation

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Solution Overview

Problem

Existing CMOS fabrication processes face challenges in achieving optimal performance of n-type and p-type field effect transistors due to the need for different channel materials, which are not adequately addressed in current nano-scale device architectures.

Innovation Solution

A method is developed to form semiconductor devices with alternating layers of selectively etchable first and second channel materials, allowing for the formation of n-type and p-type field effect transistors with distinct channel properties by etching and oxidizing exposed portions to create different caps and source/drain regions, followed by doping and metal layer deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different channel materials are used for n-type and p-type field effect transistors, then optimal performance of each transistor type is achieved, but device complexity increases due to the need for multiple material layers and selective etching processes

Engineering Contradiction:
Improvetransistor performanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The channel region is segmented into alternating layers of first channel material and second channel material, allowing selective etching to create n-type devices using one material and p-type devices using the other material from the same stack structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different channel materials are placed at different vertical positions within the channel stack, with specific materials exposed in specific device regions through selective etching, enabling locally optimized transistor performance without requiring entirely separate fabrication lines

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If alternating layers of different channel materials are formed, then n-type and p-type transistors can be fabricated on a single substrate, but manufacturing precision requirements increase due to the need for selective etching of specific layers

Engineering Contradiction:
Improvedevice type integrationVSAvoidselective etching precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Cap layers are formed on the exposed surfaces of the channel materials before etching, and these caps are subsequently selectively removed to expose the desired channel material layers for n-type or p-type device formation, enabling precise control over which material layers are accessed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cap layers act as intermediary protective structures that are temporarily formed on channel material surfaces, allowing selective etching processes to proceed without damaging unwanted channel material layers, and are removed only when needed to expose the target channel material

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of integrated chips with n-type and p-type field effect transistors having different channel materials, enhancing device performance and efficiency by optimizing transistor properties.

Implementation Method 1

forming first layer caps at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material by oxidizing exposed portions of the first material

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12520567B2Hybrid-channel nano-sheet FETs
Publication Date: 2026.01.06 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US12520567B2 patent drawing
  • US12520567B2 patent drawing
  • US12520567B2 patent drawing

AI summary

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.