Hybrid Channel Layout for Sub-10 nm Short-Channel Control
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors below the 10 nm node is exacerbated by the trade-off between critical dimension and spacing constraints in lithographic processes, leading to issues with short channel control and increased parasitic capacitance in conventional transistor architectures.
Innovation Solution
A hybrid channel layout incorporating nanowire, nanoribbon, and forksheet transistors with a self-aligned dielectric backbone or wall, allowing for increased density and improved short channel control through backside fabrication techniques, reducing parasitic capacitance and enabling efficient interconnect architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional transistor architectures are used for scaling below 10 nm, then manufacturing processes become simpler, but short channel control deteriorates and parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at sub-10nm nodes while maintaining compatibility with standard fabrication processes through sequential deposition and release techniques.
2Quantity of substance
If feature size is reduced to increase device density, then capacity increases, but lithographic spacing constraints worsen
Solution Approach 1:
By moving to vertical nanowire structures, the patent achieves higher device density through the third dimension (vertical stacking) rather than further lateral scaling. This allows maintaining larger lithographic spacing in the lateral plane while increasing effective channel width through multiple vertically stacked nanowires, thereby decoupling density requirements from lithographic resolution constraints.
Solution Approach 2:
The gate structure completely surrounds each nanowire channel, with the gate electrode nested around the channel in a concentric configuration. This gate-all-around structure provides maximum control over the channel while maintaining compact footprint, enabling high density without proportionally reducing lithographic spacing requirements.
3Device complexity
If multi-gate transistors are fabricated on bulk silicon substrates, then cost decreases and fabrication complexity reduces, but short channel control and mobility improvement are compromised
Solution Approach 1:
The patent segments the channel into multiple independent nanowires stacked vertically, with each nanowire surrounded by its own gate structure. This segmentation allows each nanowire to be independently controlled by the gate, providing superior short channel control compared to planar structures. The segmented approach also enables better mobility through optimized crystal orientation of individual nanowires while maintaining compatibility with bulk silicon fabrication processes.
Data Source
AI summary
Integrated circuit structures having a hybrid channel layout are described. A structure includes one or more gate-all-around channel structures along a track, and one or more forksheet-based channel structures along the track.