Hybrid Charge Pump Clocking for Lower Die Area Voltage Boosting
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Solution Overview
Problem
The existing charge pumps in NAND-type flash memories occupy significant die area, leading to reduced space for NAND arrays and other components, and experience voltage drops across semiconductor devices, necessitating larger and more powerful pumps to maintain output voltage, which increases die area requirements.
Innovation Solution
The use of a hybrid charge pump design incorporating depletion-mode NMOS and enhancement-mode PMOS semiconductor devices, along with a novel clocking scheme, reduces voltage drops and physical die area while maintaining or increasing output voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional charge pumps are used to generate boosted voltages, then output voltage levels can be maintained, but die area is significantly occupied
Solution Approach 1:
The patent changes the operational parameters of the charge pump by implementing a novel clocking scheme that optimizes the charging and boosting phases. This allows the charge pump to achieve the same or higher output voltage levels while reducing the required die area through more efficient parameter utilization.
Solution Approach 2:
The charge pump circuit is designed to perform multiple functions within a compact structure, including voltage charging, boosting, and regulation, thereby reducing the overall die area required while maintaining the necessary output voltage levels for NAND flash operations.
2Power
If larger and more powerful charge pumps are used to compensate for voltage drops, then output voltage can be maintained, but die area requirements increase
Solution Approach 1:
The patent converts the inherent voltage drops across semiconductor devices into a design advantage by optimizing the clocking scheme to minimize these drops. The novel clocking approach transforms what would be harmful voltage losses into efficient voltage transfer, allowing smaller charge pump structures to achieve the same output voltage.
Solution Approach 2:
The charge pump employs dynamic clocking signals that adaptively control the charging and boosting phases, optimizing performance in real-time. This dynamic operation allows the circuit to maintain high output voltage levels with reduced component size compared to static designs.
3Power
If charge pumps occupy significant real estate on NAND flash memory die, then voltage boosting can be performed, but space for NAND arrays and other components is reduced
Solution Approach 1:
The charge pump circuit is segmented into distinct functional blocks (charging phase circuitry, boosting phase circuitry, clocking circuitry) that can be optimized independently. This segmentation allows for compact layout and efficient utilization of die space while maintaining full voltage boosting capability.
Solution Approach 2:
The patent implements a nested structure where the charging circuitry and boosting circuitry are integrated in a compact arrangement, with shared components and overlapping signal paths. This nesting approach minimizes the overall footprint of the charge pump on the NAND flash memory die.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid charge pump design reduces die area usage and enhances output voltage and current levels, addressing the limitations of traditional charge pumps by minimizing voltage losses and allowing for more efficient use of memory die space.
Implementation Method 1
charge pumps configured to apply bias voltage levels to NAND arrays
Implementation Method 2
a first capacitor coupled to the first semiconductor device and configured to store charge
Data Source
AI summary
A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.