Hybrid Chip Simulation Using Legacy Silicon and C Models
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Solution Overview
Problem
Conventional chip design and development methods face challenges in early-stage system-level driver and application development due to slow C-model-based test environments and scarce, costly emulator resources, limiting progress and increasing the chip design cycle.
Innovation Solution
A software and hardware hybrid simulation method that utilizes a previous-generation physical chip and a C model to process different request features, allowing for faster simulation by dispatching tasks based on parameter configuration and request features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a C-model-based test environment is used for Windows HLK test suite and Linux VAAPI driver support, then the simulation can be performed in pre-silicon, but the simulation speed is excessively slow
Solution Approach 1:
The patent segments the simulation workload by request features into two processing paths: one for features unchanged from the previous-generation physical chip and another for new features. This segmentation allows the system to leverage existing hardware for familiar operations while using software models for new functionality, thereby significantly improving overall simulation speed without compromising completeness.
Solution Approach 2:
The patent introduces a command buffer as an intermediary mechanism between the driver and the simulation execution engine. The command buffer receives commands, identifies request features, and routes them to appropriate processing paths (previous-generation physical chip or C model). This intermediary enables efficient task dispatching and feature-based routing, resolving the contradiction between comprehensive testing and simulation speed.
2Productivity
If an emulator environment is used for customized applications, then development and debugging can be performed, but emulator resources are very scarce and costly and become available only after RTL circuit code verification is mature
Solution Approach 1:
The patent enables preliminary software development and testing before RTL circuit code verification is fully mature. By using the command buffer to route customized application requests to the previous-generation physical chip for features not changed from the prior generation, the system allows early-stage software development to proceed in parallel with hardware verification, eliminating the sequential dependency that previously existed.
Solution Approach 2:
The patent creates a dynamic simulation environment where the processing path is determined at runtime based on request features. The system can flexibly switch between using the previous-generation physical chip for unchanged features and the C model for new features, allowing emulator resources to be utilized more efficiently and available earlier in the development cycle.
3Productivity
If all tasks are dispatched to the previous-generation physical chip, then simulation speed increases, but new features cannot be properly tested
Solution Approach 1:
The patent applies local quality by differentiating the processing approach based on the specific characteristics of each request feature. For features unchanged from the previous generation, the system uses the previous-generation physical chip for fast simulation. For new features, the system uses the C model to ensure proper testing and validation. This localized differentiation resolves the contradiction between speed and adaptability.
Solution Approach 2:
The patent changes the processing parameter based on request feature characteristics. The command buffer analyzes each command's features and dynamically adjusts the execution path: using hardware acceleration for unchanged features and software modeling for new features. This parameter-based routing enables the system to maintain both high simulation speed and full feature support.
Data Source
AI summary
The present disclosure relates to a software and hardware hybrid simulation method and apparatus, a computer device, a computer-readable storage medium, and a computer program product. The method includes: acquiring an updated command group from a command buffer, the command group including: parameter configuration; disassembling a task according to the parameter configuration in the updated command group to obtain disassembled tasks; and dispatching, according to different request features, the disassembled tasks to a previous-generation physical chip and a C model for processing, wherein the request features include features that are not changed compared to the previous-generation physical chip and features that are new compared to the previous-generation physical chip. Therefore, a pre-silicon software stack development cycle can be significantly shortened, so that software development activities can be started earlier. By advancing with an architecture C model, software development can cover more application test development scenarios with higher performance requirements and can also be deployed to a local environment, making debugging easier.