Hybrid-Bonded Chip Stack Packaging to Reduce Warpage
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high structural stability and reliability due to the increased use of adhesive members, which can lead to technical issues such as failure during the fabrication process and warpage caused by thermal expansion coefficients, especially in stack-type semiconductor packages.
Innovation Solution
A semiconductor package design featuring a substrate with vias and a chip stack comprising multiple semiconductor chips bonded using metal-to-metal hybrid bonding structures, with non-conductive layers strategically placed between chips to reduce the number of adhesive layers and prevent detachment, while a mold layer encapsulates the package for added stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple adhesive members are used to attach semiconductor chips in a stack package, then the chips can be mounted and connected, but the structural stability deteriorates due to warpage caused by thermal expansion coefficients
Solution Approach 1:
The patent removes adhesive members from the bonding process between semiconductor chips and substrate. Instead of using adhesive layers, the invention employs direct metal-to-metal hybrid bonding between pads on the substrate and chips, eliminating the adhesive layer that causes warpage and stability issues during thermal cycling.
Solution Approach 2:
The patent introduces a pad structure as an intermediary element between the substrate and semiconductor chips. These pads serve as bonding interfaces that enable direct metal bonding without requiring adhesive materials, thus resolving the warpage problem while maintaining mounting capability.
2Ease of manufacture
If multiple adhesive members are used to attach semiconductor chips, then chips can be bonded together, but reliability deteriorates due to failure in the adhesive layers
Solution Approach 1:
The invention extracts and eliminates adhesive members from the bonding system. By using direct metal-to-metal hybrid bonding between substrate pads and chip pads, the patent removes the adhesive layers that are prone to failure, thereby significantly improving bonding reliability while maintaining the essential bonding function.
Solution Approach 2:
The patent employs hybrid bonding that combines different bonding mechanisms (metal diffusion bonding and eutectic bonding) at the pad interfaces. This composite bonding approach creates a more reliable connection than adhesive bonding alone, as it leverages the strengths of multiple bonding mechanisms to achieve superior bond strength and reliability.
3Ease of manufacture
If adhesive layers are used between chips, then chips can be attached, but the number of adhesive layers increases leading to more failure points
Solution Approach 1:
The patent systematically removes adhesive layers from between all chip interfaces in the stack. By implementing direct pad-to-pad metal bonding across all chip-substrate and chip-chip interfaces, the invention eliminates multiple adhesive layers that would otherwise be required, thereby reducing the total number of potential failure points in the package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances structural stability and reliability by minimizing adhesive-related failures and warpage issues, allowing for easier bonding processes and improved mechanical durability of the semiconductor package.
Implementation Method 1
a first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate, wherein the first chip pad and the substrate pad each comprise the same metallic material and form a first single structure or layer
Implementation Method 2
a second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip, wherein the second chip pad and the third chip pad each comprise the same metallic material and form a second single structure or layer
Data Source
AI summary
A semiconductor package including a substrate comprising a plurality of vias; a chip stack on the substrate; and a mold layer on the substrate and on at least a portion of the chip stack. The chip stack includes a first semiconductor chip; second semiconductor chips stacked on the first semiconductor chip; a third semiconductor chip on the uppermost one of the second semiconductor chips; and non-conductive layers between the first semiconductor chip and the second semiconductor chips. A first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate. A second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip. Each of the second semiconductor chips is electrically connected to another of the second semiconductor chips or the first semiconductor chip.