Hybrid Chip Assembly With Carrier-Isolated Thermal Alignment
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Solution Overview
Problem
Modern devices with semi-conductor chips face issues with heat generation leading to misalignment due to thermal expansion, and high heat transfer between chips, which can cause adhesive fracture and inefficient operation.
Innovation Solution
The apparatus configures two chips such that they are free of direct contact by using a first chip with a cavity and a second chip affixed to a carrier, which is then mechanically anchored to the first chip, thereby reducing heat transfer and avoiding over-constraint from multiple bonded joints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If two chips are directly bonded together with multiple adhesive joints, then mechanical strength and alignment are improved, but heat transfer between chips increases and adhesive fracture risk increases
Solution Approach 1:
The patent divides the connection system into separate functional components: a first chip, a carrier, and a second chip. The carrier acts as an intermediary that mechanically supports the second chip while being attached to the first chip, segmenting the thermal and mechanical pathways. This segmentation reduces direct heat transfer between chips while maintaining structural integrity through the carrier's mechanical anchoring.
Solution Approach 2:
The carrier serves as an intermediary component between the two chips. It provides mechanical support and positioning for the second chip while being attached to the first chip through a single bonded joint. This intermediary structure reduces thermal crosstalk by breaking the direct thermal path between chips, while still maintaining optical alignment and mechanical strength through its positioning features.
2Manufacturing precision
If multiple bonded joints are used to align chips, then alignment precision is improved, but adhesive fracture due to thermal expansion increases
Solution Approach 1:
The connection system is segmented into the carrier and chip assembly, which is attached to the first chip as a single unit. This reduces the number of bonded joints from multiple (between each chip and substrate) to one (between carrier and first chip), minimizing the number of adhesive interfaces that could fracture due to thermal expansion differential.
Solution Approach 2:
The carrier acts as a mediator that absorbs and distributes thermal stress. By providing a rigid mechanical support structure with positioning features, the carrier maintains alignment precision while reducing the burden on adhesive bonds. The single bonded joint between carrier and first chip experiences reduced thermal stress compared to multiple joints in direct chip-to-chip bonding.
3Device complexity
If chips are in direct contact, then thermal management is simplified, but heat transfer between chips increases causing thermal crosstalk
Solution Approach 1:
The carrier serves as a thermal intermediary with lower thermal conductivity than direct chip-to-chip contact. It provides mechanical support and positioning while acting as a thermal barrier that reduces heat transfer between chips. The carrier's material properties and geometry are designed to minimize thermal crosstalk while maintaining structural function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration mitigates heat transfer between the chips, maintains alignment by avoiding adhesive fracture, and allows for efficient operation with reduced thermal crosstalk, thereby improving the performance and longevity of the chips.
Implementation Method 1
disposing a structural adhesive onto an elevated surface of a first chip... contacting a carrier with the structural adhesive... curing the structural adhesive so that the carrier and host chip are mechanically anchored
Implementation Method 2
connecting the lateral surface of the cavity and a lateral surface of the second chip with an optical adhesive
Implementation Method 3
The second chip is thermally connected with the carrier at a bottom surface of the carrier and a top surface of the second chip
Implementation Method 4
The protrusion may be present to ensure a known adhesive gap thickness so that the apparatus is athermal between the components
Data Source
AI summary
A method including disposing a structural adhesive onto an elevated surface of a first chip that includes a cavity disposed below the elevated surface. The method includes contacting a carrier with the structural adhesive. The carrier includes a second chip that optically aligns with a lateral surface of the cavity. The method includes curing the structural adhesive so that the carrier and host chip are mechanically anchored. An apparatus includes a first chip including a cavity located between lateral walls of the first chip and a carrier mechanically anchored with the first chip at a top portion of the lateral walls. The carrier includes a second chip that optically aligns with the first chip at a side portion of one of the lateral walls. The first and second chips are free of contact at a bottom surface of the second chip and a bottom surface of the cavity.