Hybrid Compute-in-Memory Array With Reduced-Range ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Compute-in-memory architectures face challenges in achieving high computation speed and power efficiency due to the need for high-resolution analog-to-digital converters, which increase power consumption and reduce operating speed, especially in edge and server machine learning applications.
Innovation Solution
A hybrid compute-in-memory architecture that combines traditional digital computing speed with the power savings of compute-in-memory computation by performing partial multiplications and accumulations in the analog domain and digitizing results using reduced dynamic range analog-to-digital converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution ADC is used to achieve the same precision as traditional digital computing, then measurement precision is improved, but power consumption increases and operating speed reduces
Solution Approach 1:
The patent divides the computation into two domains: analog domain for multiplication and partial accumulation (using capacitor arrays), and digital domain for final accumulation and addition (using digital adders). This segmentation allows the use of reduced-resolution ADCs while maintaining overall computational precision, thereby reducing ADC power consumption without sacrificing measurement precision.
Solution Approach 2:
The patent changes the precision parameter of ADCs from high-resolution to reduced-resolution by leveraging the hybrid compute-in-memory architecture. The analog-to-digital conversion only needs to capture the analog multiplication results with reduced precision since the final precision is achieved through digital accumulation of multiple partial results, thus reducing power consumption.
2Measurement precision
If high-resolution ADC is used to achieve the same precision as traditional digital computing, then measurement precision is improved, but operating speed reduces
Solution Approach 1:
The computation is segmented such that analog multiplication and partial accumulation occur in parallel across multiple capacitor arrays, while digital accumulation and addition are performed in the digital domain. This segmentation eliminates the bottleneck of high-resolution ADC conversion by reducing the precision requirements, thereby increasing operating speed.
Solution Approach 2:
The patent performs partial accumulation in the analog domain using capacitor arrays before digital conversion. This partial action in the analog domain reduces the dynamic range required for ADC conversion, allowing the use of faster, lower-resolution ADCs that do not slow down the overall operating speed.
3Productivity
If traditional digital architecture is used to achieve high computation speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent replaces traditional digital mechanical switching and data movement with analog charge accumulation in capacitor arrays. The analog domain performs multiplication and partial accumulation through charge sharing, eliminating the need for data transport between memory and processing units, thus reducing power consumption while maintaining high computation speed.
Solution Approach 2:
The patent changes the computational domain from purely digital to a hybrid analog-digital system. Analog parameters (charge, voltage) are used for multiplication and partial accumulation, which are inherently more power-efficient for compute-intensive operations, while digital parameters are used for final accumulation and control functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid architecture achieves high computation speed with reduced power consumption by partial accumulation across subsets of channels, utilizing foundry bitcells for filter weight storage and minimizing ADC power demands.
Implementation Method 1
compute-in-memories perform multiplication and summation operations in the analog domain such as by accumulating charge from a plurality of capacitors
Data Source
AI summary
A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.