Hybrid Integrated Circuit Architecture Using Embedded Chip
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Solution Overview
Problem
There is a need for an electronic assembly or hybrid component that is easier and more economical to manufacture with high manufacturing yields than those currently known.
Innovation Solution
An electronic assembly is created by connecting a microelectronic circuit in a wafer to a microelectronic circuit in a chip, where the chip is embedded in a metal-filled cavity of the wafer, with contact pads on opposite surfaces and a conductor connecting these pads, allowing for a high-performance integration of components like GaN RF MMICs into silicon-based carrier wafers with high yields and short manufacturing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If microelectronic circuits are fabricated separately and assembled together, then manufacturing flexibility and circuit performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the hybrid circuit into separate fabricatable modules (first circuit module on first substrate, second circuit module on second substrate) that can be independently manufactured using different processes and materials, then assembled together. This segmentation enables manufacturing flexibility while managing complexity through standardized interface definitions.
Solution Approach 2:
The patent embeds one circuit module within a cavity of the other module's substrate (first circuit module embedded in cavity of second substrate, or vice versa). This nesting approach reduces overall assembly complexity by integrating multiple functions into a compact hierarchical structure while maintaining the ability to fabricate modules separately.
2Productivity
If microelectronic circuits are fabricated separately, then fabrication yields are improved, but manufacturing time and process complexity increase
Solution Approach 1:
The patent performs preliminary fabrication of circuit modules on separate substrates using optimized processes for each module type, achieving high fabrication yields. The modules are prepared with pre-defined interfaces and embedding structures, allowing rapid final assembly without time-consuming in-situ fabrication steps.
Solution Approach 2:
The patent combines multiple fabrication advantages by allowing different modules to be manufactured using their optimal processes separately, then merging them through standardized assembly operations. This merging approach maintains high yields while reducing overall manufacturing time compared to monolithic fabrication.
3Reliability
If different materials and manufacturing processes are used for different circuits, then circuit performance is improved, but manufacturing precision and integration difficulty increase
Solution Approach 1:
The patent allows each circuit module to be fabricated with local quality optimized for its specific function and material requirements. Different substrates can use different materials and processes appropriate to their circuit requirements, while the embedding interface ensures precise integration through geometric constraints and standardized connection protocols.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high-performance integrated circuits into carrier wafers with improved manufacturing efficiency and yield, allowing for the production of compact, high-performance electronic assemblies with reduced manufacturing complexity and cost.
Implementation Method 1
a conductor connects said contact pads
Data Source
AI summary
An electronic assembly comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising an integrated circuit contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by direct contact of at least a side surface of said component chip with an attachment metal that fills at least a portion of said through-wafer cavity; said component chip comprising at least one component contact pad on said component chip bottom surface; and a conductor connecting said integrated circuit contact pad and said component contact pad.