Hybrid Integrated Circuit Device Segmentation for Lithography Yield
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Solution Overview
Problem
The incongruity in lithographic process technologies for integrated circuits leads to increased costs and manufacturing complications, as not all components of an FPGA shrink with new lithographic advancements, resulting in disparate component sizes and higher yield rates for sensitive semiconductor processing.
Innovation Solution
A hybrid integrated circuit device is formed by separating components into two groups based on lithographic dimensions, with one die manufactured using a smaller lithography for advanced features and another using a larger lithography for cost-effective production, allowing for interconnects and circuitry to couple the dies for electrical communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If state-of-the-art lithography is used for manufacturing FPGA components, then manufacturing precision is improved, but manufacturing cost increases and yield rate decreases due to higher sensitivity to processing variations
Solution Approach 1:
The FPGA device is divided into two separate dies: a first die containing components requiring state-of-the-art lithography (e.g., configurable logic blocks, interconnect structures) and a second die containing components that can be manufactured with less aggressive lithography (e.g., I/O blocks, memory elements). This segmentation allows each die to be optimized for its specific lithographic requirements, improving overall yield while maintaining manufacturing precision where needed.
Solution Approach 2:
Components that do not require cutting-edge lithography are extracted from the main FPGA die and placed on a separate second die. This extraction allows the first die to focus solely on components that benefit from state-of-the-art lithography, thereby improving yield rate by avoiding the sensitivity issues that affect the entire die when all components are manufactured together.
2Manufacturing precision
If state-of-the-art lithography is used for all components, then manufacturing precision is improved, but manufacturing cost increases due to higher cost per unit area
Solution Approach 1:
The device is segmented into two dies with different lithographic specifications. The first die uses state-of-the-art lithography only where necessary for high-precision components, while the second die uses less expensive, less aggressive lithography for components that do not require such precision, thereby reducing overall manufacturing cost while maintaining necessary precision.
Solution Approach 2:
Different lithographic qualities are applied to different regions/components of the device. High-precision state-of-the-art lithography is applied locally to components that require it (such as configurable logic and interconnect), while less expensive lithography is used for other components, optimizing the balance between manufacturing precision and cost.
3Device complexity
If all components are manufactured on the same die, then device complexity is reduced, but manufacturing complications increase due to disparate component size requirements
Solution Approach 1:
The device is segmented into two separately manufactured dies that are then integrated through stacking and bonding. This segmentation allows each die to be optimized for its specific component requirements, simplifying the manufacturing process for each individual die while enabling the overall device to achieve high integration through the stacking architecture.
Data Source
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AI summary
Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).