Hybrid On-Chip Clock Controller for At-Speed Scan Testing
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Solution Overview
Problem
As integrated circuits become faster and more complex, traditional scan-based testing methods struggle to detect defects like high impedance shorts and crosstalk, leading to increased testing time due to the need for at-speed scan testing at functional clock frequencies, which is challenging with external Automatic Test Equipment (ATE) providing slow clock speeds.
Innovation Solution
The implementation of a hybrid on-chip clock controller architecture that dynamically switches between test clock pulse control and OCC clock chain control modes, using an OCC Clock Chain engine to generate higher frequency test clock signals, reducing the need for wait cycles and enabling efficient at-speed scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan-based testing methods are used, then test coverage for basic faults is achieved, but testing time increases significantly when at-speed scan testing is required
Solution Approach 1:
The patent implements a dynamic clock controller that switches between different clocking modes (slow clock mode for setup/teardown, fast clock mode for capture) based on the testing phase. This allows the system to adapt clock frequencies dynamically, enabling at-speed scan testing without excessive wait cycles, thus reducing overall testing time while maintaining comprehensive defect detection capability.
2Stability of the object's composition
If external ATE provides slow clock speeds, then setup and teardown operations are stable, but capture operations must wait for external clock signals causing time loss
Solution Approach 1:
The patent segments the clock control functionality into separate slow clock mode and fast clock mode operations. The slow clock mode handles setup and teardown operations using external ATE clock signals, while the fast clock mode handles capture operations using internal high-frequency clock signals. This segmentation allows each phase to operate at optimal speeds without compromising stability.
Solution Approach 2:
The clock controller dynamically switches between slow clock mode and fast clock mode based on the testing phase. During setup and teardown, it uses slow clock mode for stability. During capture, it switches to fast clock mode to eliminate wait cycles and reduce time loss. This dynamic adaptation resolves the contradiction between stability and speed.
3Productivity
If internal fast clock pulses are generated at functional frequencies, then at-speed scan testing efficiency is improved, but clock control complexity increases
Solution Approach 1:
The patent implements a universal clock controller that performs multiple functions: it controls setup/teardown operations, generates fast clock pulses for capture operations, and manages mode switching between slow and fast clock modes. By consolidating these functions into a single multi-functional controller, the patent achieves at-speed scan testing efficiency without proportionally increasing complexity.
Data Source
AI summary
Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.