Hybrid Clock Multiplexer for Wide-Range Jitter and Power Control
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Solution Overview
Problem
Conventional clock multiplexers face challenges in combining resonant and CMOS clocking techniques in a single device, leading to suboptimal power and jitter performance across a wide range of data rates, particularly at high speeds exceeding 100 Gbps, due to limitations in power efficiency, area usage, and performance.
Innovation Solution
A hybrid clock multiplexer employing a resonant-CMOS hybrid clocking architecture with a single differential inductor core, allowing for reconfiguration between resonant clocking for high-speed paths and CMOS clocking for low-speed paths, thereby enabling efficient power management and improved jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock multiplexer uses conventional CMOS clocking for all data rates, then device complexity is reduced, but jitter performance and power efficiency deteriorate at high speeds exceeding 100 Gbps
Solution Approach 1:
The clock multiplexer dynamically reconfigures its internal architecture based on the operating data rate. At high speeds (>100 Gbps), it switches to resonant clocking mode with coupled inductors to achieve low jitter performance. At lower speeds, it operates in CMOS mode for power efficiency. This dynamic adaptation resolves the contradiction by optimizing jitter performance only when needed at high data rates.
Solution Approach 2:
The patent changes the electrical parameters of the clock multiplexer by switching between two distinct operating modes: resonant mode with specific inductor coupling for high-speed operation, and CMOS mode for lower speeds. This parameter change allows the device to achieve excellent jitter performance (>100 Gbps) without sacrificing power efficiency at lower rates, resolving the performance-complexity contradiction.
2Reliability
If a hybrid resonant-CMOS clocking architecture is implemented, then jitter performance and power efficiency are improved across wide data rates, but device complexity and area usage increase
Solution Approach 1:
The clock multiplexer is designed as a universal device that can perform both resonant clocking and CMOS clocking functions within a single architecture. It supports multiple data rates from low-speed to high-speed (>100 Gbps) operations, achieving both power efficiency and low jitter performance across the entire range. This multi-functionality resolves the contradiction by eliminating the need for separate dedicated circuits for different speed ranges.
Solution Approach 2:
The architecture dynamically adapts between resonant and CMOS operating modes based on the required data rate. Control logic automatically selects the appropriate clocking mode, enabling the device to achieve optimal power efficiency at lower speeds and optimal jitter performance at high speeds without requiring multiple static architectures.
3Reliability
If resonant clocking is used for high-speed paths and CMOS clocking for low-speed paths within the same multiplexer, then power performance and jitter are optimized, but the number of components and area increase
Solution Approach 1:
The patent merges resonant clocking components (inductors, resonant tanks) and CMOS clocking components (buffers, switches) into a single integrated clock multiplexer architecture. The inductors are shared between both modes, and the switching mechanism allows seamless transition between resonant and CMOS operation. This merging achieves excellent clock quality across all data rates while minimizing area by avoiding duplicate separate circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid clock multiplexer achieves significant improvements in jitter and power performance by allowing different clocking types within a single multiplexer, reducing loading of unused paths and enhancing clock quality across various data rates, while supporting multi-rates and backward compatibility.
Implementation Method 1
at least one differential inductor formed of the first inductor and the second inductor in response to the first switch being in a closed state, where the device outputs a resonant clock signal
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
In some implementations, the device (100) includes a first circuit (102, 103) receiving an input signal (CKP1, CKN1) having a first frequency, the first circuit including a first node (106) and a second node (108). The device includes a second circuit (104, 105) receiving an input signal (CKP2, CKN2) having a second frequency different from the first frequency, the second circuit including a first node (110) and a second node (112), and a first inductor (L1) coupled between the first node of the first circuit and the first node of the second circuit. The device further includes a second inductor (L2) coupled between the second node of the first circuit and the second node of the second circuit.