Hybrid Multiphase Clock Generation for Power and Phase Accuracy
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Solution Overview
Problem
Conventional multiphase clock generation techniques suffer from high power consumption and phase inaccuracy, with exclusively passive methods degrading phase accuracy and exclusively active methods consuming more power and exhibiting higher random variations.
Innovation Solution
The proposed solution involves a hybrid multiphase clock generation apparatus that combines active and passive circuits in a cascade configuration, using injection-locked oscillators as active components and RC polyphase filters as passive components, arranged alternately in series to generate phase-shifted clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If exclusively passive RC polyphase filters are used for multiphase clock generation, then power consumption is reduced, but phase accuracy is degraded
Solution Approach 1:
The patent combines passive RC polyphase filter stages with active injection-locked oscillator stages in a hybrid cascade configuration. The passive stages provide power-efficient phase shifting while the active ILO stages compensate for phase errors and maintain accuracy, thus merging the advantages of both approaches.
Solution Approach 2:
Different stages in the cascade are assigned different functions: passive RC stages perform initial phase splitting with low power consumption, while active ILO stages provide local phase correction and buffering to maintain accuracy. Each stage has optimized local characteristics suitable for its specific role in the overall system.
2Measurement precision
If exclusively active circuits are used for multiphase clock generation, then phase accuracy is improved, but power consumption increases
Solution Approach 1:
Instead of using active circuits for all phase shifting operations, the patent applies active ILO stages only where necessary - specifically for phase correction and buffering at critical points in the cascade. The majority of phase shifting is accomplished by passive stages, reducing overall power consumption while maintaining accuracy where it matters most.
3Measurement precision
If exclusively active circuits are used for multiphase clock generation, then phase accuracy is improved, but random variation increases
Solution Approach 1:
The hybrid architecture merges the low random variation characteristics of passive RC circuits with the high phase accuracy of active ILO circuits. The passive stages provide stable, low-noise phase splitting while the active stages correct phase errors without introducing excessive random variation, achieving a balance between accuracy and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This hybrid approach reduces power consumption and improves phase accuracy compared to exclusively active methods, while maintaining better accuracy than exclusively passive methods, thus enabling improved multiphase clock generation.
Implementation Method 1
The cascade of coupled clock generation circuits comprises a plurality of injection-locked oscillators and RC polyphase filters coupled alternately in series
Implementation Method 2
The cascade of coupled clock generation circuits comprises a plurality of injection-locked oscillators and RC polyphase filters coupled alternately in series
Data Source
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AI summary
An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.