Hybrid Clock Switching to Cut PLL Power in Data Transfer
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Solution Overview
Problem
Phase-locked loops (PLLs) consume significant power due to their large number of components, making them unsuitable for applications like mobile devices where battery life is a concern, especially for high-speed data transfers.
Innovation Solution
A hybrid clock system that operates in both normal and power-saving modes, using a PLL for high-speed data transfers and bypassing it for low-speed activity, reducing power consumption by directly connecting the reference clock to the data transfer circuit, and adjusting the reference clock frequency to maintain performance in power-saving mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a PLL is used for high-speed data transfers, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between two operational modes: using a PLL for high-speed data transfers and bypassing the PLL for low-speed transfers. This dynamic adaptation allows the system to optimize performance based on actual data transfer requirements, reducing unnecessary power consumption during low-speed operations while maintaining high-speed capability when needed.
Solution Approach 2:
The system changes the operational parameter by switching the clock source selection based on data transfer speed requirements. When high-speed transfer is detected, the PLL is enabled; when low-speed transfer is detected, the system switches to using the reference clock directly, thereby changing the power consumption parameter to match the performance requirements.
2Speed
If a PLL is used for clock multiplication, then operating frequency is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the clock multiplication approach based on the required operating frequency. For high-frequency operations, the PLL performs clock multiplication; for lower-frequency operations, the system bypasses the PLL and uses the reference clock with appropriate division, thereby optimizing power consumption while maintaining required operating frequencies.
Solution Approach 2:
The system changes the clock generation parameter by switching between PLL-based multiplication and reference clock-based operation depending on the required output frequency, allowing the system to maintain high-frequency capability when needed while reducing power consumption during lower-frequency operations.
3Speed
If the reference clock frequency is increased to compensate for bypassing the PLL, then data transfer speed is maintained, but power consumption increases
Solution Approach 1:
The system carefully adjusts the reference clock frequency parameter to the minimum necessary value that still allows adequate data transfer performance when the PLL is bypassed. This optimized parameter setting maintains acceptable data transfer speed while minimizing power consumption during low-speed operations.
Data Source
AI summary
A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.