Hybrid Clock Data Recovery for Fast Locking and Noise Resistance
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Solution Overview
Problem
Current clock data recovery circuits, whether analog or digital, face challenges such as failure to lock phase during frequency deviations, accumulation of noise during data transitions, and limited phase tracking ability, leading to bit errors and unsatisfactory linearity.
Innovation Solution
A clock data recovery apparatus and method incorporating a phase detection circuit, digital filter, phase-interpolating circuit, and oscillator circuit that samples data signals with multiple reference clock signals, generates phase detection results, performs phase adjustments, and generates injection clock signals to stabilize clock data recovery, combining the advantages of both analog and digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an analog clock data recovery circuit is used, then the circuit can lock phase quickly, but it fails to lock when frequency deviation occurs and accumulates noise during long periods without data transition
Solution Approach 1:
The patent combines analog and digital circuit architectures into a hybrid system. The phase detector uses analog components for quick response, while the digital filter and phase interpolator provide stable, noise-resistant phase adjustment. This merging allows the system to achieve both fast locking and reliable operation under frequency deviation and no-data conditions.
Solution Approach 2:
The patent introduces a digital filter as an intermediary between the phase detector and the phase interpolator. This digital filter accumulates phase error information over time, providing a stable, noise-filtered control signal that prevents noise accumulation in the analog circuit while maintaining effective phase correction capability.
2Reliability
If a digital clock data recovery circuit is used, then noise accumulation is reduced, but the delay time is longer and phase tracking ability is limited under large frequency deviation
Solution Approach 1:
The hybrid architecture merges digital noise resistance with analog speed. The digital filter provides noise filtering, while the analog phase interpolator and oscillator provide fast response. This combination reduces recovery delay time while maintaining strong noise resistance capability.
Solution Approach 2:
The patent makes the system dynamically adaptable by using a phase-locked loop that continuously adjusts the phase of the recovered clock based on real-time phase error detection. This dynamic adjustment allows the system to track phase changes quickly even under large frequency deviation, overcoming the static limitations of pure digital circuits.
3Device complexity
If a digital clock data recovery circuit is used, then the circuit structure is simplified, but the linearity performance is not satisfying
Solution Approach 1:
The digital filter acts as an intermediary that accumulates phase error information and generates smooth control signals for the phase interpolator. This intermediary processing improves linearity by preventing abrupt phase changes and reducing quantization effects, while the overall circuit structure remains relatively simple.
Solution Approach 2:
The patent changes the operating parameters of the phase interpolator based on the accumulated phase error from the digital filter. By dynamically adjusting the phase interpolation ratio according to the filtered error signal, the system achieves better linearity performance while maintaining circuit simplicity.
Data Source
AI summary
The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.