Hybrid Clocking for Packetized Audio Over Power-Line Conductors
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Solution Overview
Problem
Existing audio transmission systems using Ethernet and Power-Line Communication (PLC) technologies face reliability issues due to latency and jitter in PLC devices, leading to poor clock synchronization and decoding errors in packetized audio streams.
Innovation Solution
A distributed amplification system that combines Ethernet audio and PLC signals over a common conductor, using a single master clock to synchronize both Ethernet and PLC transmitters, and employs PLC demodulation receivers at endpoints to recover and align the master clock, adjusting for latency and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packet-based clock synchronization schemes (AES67) are used over Ethernet, then audio data transmission can be achieved, but reliability deteriorates when packets pass through PLC devices due to latency and jitter
Solution Approach 1:
The patent introduces an intermediary clock synchronization mechanism that operates at the physical layer through PLC signaling. This intermediary system provides a dedicated clock reference path that is independent of the packetized audio data path, thereby mediating the synchronization problem caused by PLC-induced latency and jitter in the Ethernet packet path.
Solution Approach 2:
The patent segments the clock synchronization function from the audio data transmission path. Instead of relying solely on packetized clock information embedded in audio streams, the system separates clock distribution into a dedicated PLC-based physical layer signaling path, allowing independent optimization of each path's reliability.
2Measurement precision
If a single master clock synchronizes both Ethernet and PLC transmitters, then clock alignment is improved, but system complexity increases
Solution Approach 1:
The master clock device performs multiple functions: it generates the master clock signal, distributes it through both Ethernet and PLC interfaces, and provides reference timing for both audio data and clock synchronization. This multi-functionality reduces the need for separate synchronization devices, thereby managing complexity while achieving precise alignment.
3Measurement precision
If PLC demodulation receivers recover the master clock, then decoding accuracy is improved, but processing complexity increases
Solution Approach 1:
The master clock is embedded in the PLC signal transmission in advance, allowing the demodulation receiver to recover the clock reference before audio data processing. This preliminary clock recovery enables subsequent audio decoding to proceed with accurate timing reference, reducing the need for complex post-processing synchronization adjustments.
Data Source
AI summary
A distributed amplification and packetized audio transmission system for clock synchronization and alignment between an audio/power source and endpoints with dedicated amplifiers and speakers. An Ethernet audio signal is combined with a Power-Line Communications (PLC) signal for transmission from the source to the endpoints over a common conductor. A single master clock in the source synchronizes the Ethernet audio transmitter with the PLC transmitter. Each end-point has a PLC receiver to recover the master clock for use by its Ethernet audio receiver to provide reliable clock synchronization between the source clock and the endpoint clocks. The endpoints can adjust and re-timestamp the PTP packetized clock based upon symbol and timing information from the PLC receiver.