Hybrid Cloud EDA Partitioned Netlist Extraction
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Solution Overview
Problem
Current electronic design automation (EDA) systems face significant challenges in processing time and resource efficiency due to the increasing complexity of integrated circuit (IC) layouts, which can take several days or weeks to simulate and require high-performance computer systems.
Innovation Solution
A system and method that partitions IC layouts into sub-regions for parallel netlist extraction and circuit simulation, eliminating the need for merging sub-region netlists and partitioning merged netlists, and utilizes cloud computing with pipelining and serialization to accelerate the EDA process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sequential EDA processing is used on complete IC layouts, then simulation accuracy is maintained, but processing time increases to several days or weeks and resource requirements increase
Solution Approach 1:
The patent divides the complete IC layout into multiple layout sub-regions, each processed independently to generate separate netlists. This segmentation enables parallel processing of different sub-regions simultaneously, dramatically reducing overall simulation time while maintaining the ability to produce an integrated final result
Solution Approach 2:
The patent transitions from single-system sequential processing to multi-system parallel processing by distributing layout sub-regions across multiple computer systems. This dimensional shift from one-dimensional sequential execution to multi-dimensional parallel execution accelerates processing while cloud computing resources provide scalable capacity
2Reliability
If traditional EDA processing is used, then complete circuit simulation is performed, but processor and memory requirements increase, requiring the most expensive computer systems
Solution Approach 1:
By segmenting the IC layout into sub-regions and generating separate netlists for each, the patent reduces the computational burden on individual computer systems. Each system processes only a portion of the total circuit, requiring less processor power and memory while maintaining overall simulation completeness through integration of all sub-region results
Solution Approach 2:
The patent creates a multi-functional processing architecture where multiple computer systems can independently process different layout sub-regions using the same EDA toolset. This universal approach allows standard systems to perform specialized sub-tasks, eliminating the need for single ultra-high-performance systems and enabling flexible resource allocation
3Reliability
If netlists from multiple layout sub-regions are merged before simulation, then complete circuit behavior is captured, but processing time increases due to the merging step
Solution Approach 1:
Instead of the traditional approach of merging netlists first and then simulating, the patent inverts the sequence by simulating each sub-region netlist independently first and then merging the simulation results. This reversal eliminates the time-consuming netlist merging step while preserving circuit simulation accuracy through result integration
Data Source
AI summary
Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.