Hybrid Computing System Parallelization Architecture

The patent divides the monolithic shared memory into multiple memory banks (first memory bank, second memory bank, etc.) that can be accessed independently by different processors. This segmentation allows parallel memory accesses without conflicts, as each processor can access different memory banks simultaneously, thereby resolving the Memory Wall problem while maintaining implementation simplicity.

The patent introduces a controller as an intermediary between processors and memory banks. The controller automatically manages memory allocation, access coordination, and data synchronization between processors and memory banks, eliminating the need for complex manual synchronization programming while maintaining efficient separate memory access.

The patent implements local memory banks attached to each processor, allowing processors to access their local memory banks with minimal latency. Data is pre-loaded and cached in local memory banks before being needed, reducing the need for frequent accesses to remote memory banks and thereby minimizing access time penalties while maintaining NUMA flexibility.

The patent extracts the associative memory function from the main data flow architecture and implements it as a separate, optional component. Only essential data requiring associative search is stored in associative memory, while the majority of processed data is stored in conventional memory banks, significantly reducing the size and energy consumption of associative memory while maintaining necessary data storage capacity.

The patent implements a dynamic execution model that can switch between data flow mode and instruction flow mode based on program requirements. The system dynamically selects the appropriate execution mode for different computational stages, allowing automatic parallelization when beneficial while maintaining controlled sequential execution when needed to prevent deadlocks, thus providing both high parallelism and reliability.