Hybrid Copper Interconnects for BEOL Gap-Fill
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Solution Overview
Problem
As integrated chip components are scaled down, gap-fill issues arise in copper damascene processes for BEOL metallization layers, leading to voids in metal wires and vias, which compromise the reliability of the chip due to difficulties in filling openings with minimum dimensions less than 30 nm.
Innovation Solution
The use of different conductive materials, such as cobalt or tungsten, for metal interconnect structures with smaller widths and copper for larger widths within the same BEOL metallization layer, mitigates gap-fill problems by filling small and large openings effectively without compromising electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper damascene process is used for BEOL metallization, then electrical conductivity is improved, but gap-fill issues occur leading to voids in small openings less than 30 nm
Solution Approach 1:
The patent applies different conductive materials to different regions based on opening size: cobalt or tungsten for small openings (less than 30 nm) where gap-fill is critical, and copper for larger openings where conductivity is prioritized. This local differentiation resolves the contradiction by matching material properties to specific spatial requirements within the BEOL metallization layer.
Solution Approach 2:
The patent uses a composite approach by combining multiple conductive materials (cobalt, tungsten, and copper) within the same BEOL metallization layer. Each material is strategically placed in specific regions to overcome the limitations of using a single material, thereby achieving both reliable gap-fill in small openings and high electrical conductivity in larger structures.
2Productivity
If opening size is reduced below 30 nm for scaling, then device density is improved, but gap-fill capability deteriorates leading to void formation
Solution Approach 1:
The patent selectively applies cobalt or tungsten materials specifically to small openings less than 30 nm where gap-fill challenges arise due to scaling, while using copper for larger openings. This localized material selection ensures that the critical gap-fill requirement is met in scaled-down regions without compromising the overall device density improvements.
3Manufacturing precision
If different conductive materials are used for different opening sizes, then gap-fill capability is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the BEOL metallization process into distinct stages: first forming small openings and filling them with cobalt or tungsten, then forming larger openings and filling them with copper. This segmentation of the manufacturing process allows each material to be optimized for its specific application, improving gap-fill capability while managing process complexity through structured sequencing.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure over a substrate, and a first interconnect structure arranged within the dielectric structure. A lower interconnect structure is arranged within the dielectric structure. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials. The first interconnect structure continuously extends from directly over a topmost surface of the lower interconnect structure facing away from the substrate to along opposing outer sidewalls of the lower interconnect structure.