Hybrid Copper Bonding Structure for Thin Semiconductor Packages
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Solution Overview
Problem
Existing semiconductor packages face issues with adhesion between semiconductor chips and redistribution layers, void formation, and interface delamination, which affect electrical connectivity and increase vertical thickness.
Innovation Solution
A semiconductor package with a multi-layer bonding layer structure, utilizing hybrid copper bonding (HCB) processes to enhance adhesion and reduce vertical thickness, and silicon oxide molds to prevent voids and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional single-layer bonding structure is used, then the manufacturing process is simple, but the adhesion between semiconductor chips and redistribution layers is insufficient
Solution Approach 1:
The bonding layer is divided into multiple sub-layers (first bonding layer, second bonding layer, third bonding layer) with different materials and functions. Each sub-layer addresses specific adhesion challenges between different interfaces (RDL-bonding, bonding-chip, chip-mold), thereby improving overall adhesion strength while maintaining manageable complexity through functional segmentation.
Solution Approach 2:
The patent employs a composite bonding layer structure combining different materials: copper-containing bonding layers for electrical conductivity and metallurgical bonding, and oxide-based bonding layers for adhesion and void prevention. This multi-material composite approach enhances interfacial adhesion strength between dissimilar materials (copper, silicon, mold compound) that cannot be achieved with a single material system.
2Reliability
If conventional bonding processes are used, then the manufacturing process is straightforward, but voids form between bonding layers and semiconductor chips
Solution Approach 1:
The patent introduces a porous oxide layer (e.g., porous silicon oxide) within the bonding structure that acts as a void-absorbing layer. This porous material captures and accommodates voids formed during the bonding process, preventing them from compromising electrical connections, thereby improving reliability while managing the complexity through targeted porous material placement.
Solution Approach 2:
The oxide-based bonding layer serves as an intermediary between the copper-containing bonding layers and the semiconductor chip. This intermediate layer facilitates controlled void management, provides a transition zone that accommodates thermal expansion differences, and ensures reliable electrical pathways are maintained despite the presence of voids in the bonding interface.
3Strength
If conventional bonding processes are used, then the manufacturing process is simple, but interface delamination occurs between mold and via
Solution Approach 1:
The patent incorporates an oxide-based bonding layer in advance during the bonding structure formation, before the mold is applied. This preliminary oxide layer is specifically positioned to prevent delamination at the mold-via interface, proactively addressing the adhesion challenge before it occurs during subsequent packaging steps, thereby improving interface strength while managing complexity through advance material placement.
4Strength
If thicker bonding layers are used to improve adhesion, then electrical connection reliability improves, but vertical package thickness increases
Solution Approach 1:
The patent applies different material compositions and thicknesses to different regions and functions within the bonding layer structure. The copper-containing layers provide localized electrical conductivity and metallurgical bonding, while thinner oxide layers provide localized adhesion and void prevention. This local optimization of material properties achieves high adhesion strength without requiring uniformly thick bonding layers throughout, thereby reducing overall package thickness while maintaining strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves adhesion between semiconductor chips and redistribution layers, prevents void formation, and ensures reliable electrical connections while reducing the overall package thickness.
Implementation Method 1
a first mold disposed on the first bonding layer structure and a sidewall of the first semiconductor chip, and including an oxide
Data Source
AI summary
A semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a first bonding layer structure including a first bonding pattern structure disposed on the first RDL, a first semiconductor chip disposed on the first bonding layer structure, and a first mold disposed on the first bonding layer structure and a sidewall of the first semiconductor chip, and including an oxide.