Hybrid Copper Bonding Interface for Reliable Chip Stacking

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Solution Overview

Problem

Existing semiconductor chip structures face challenges in achieving high bonding reliability when bonding a first semiconductor chip to a second semiconductor chip, which can result in poor performance of the chip structures.

Innovation Solution

A semiconductor chip structure is designed with a first semiconductor chip and a second semiconductor chip, where the first chip includes a first final wiring layer with a bonding wiring layer containing fine grain copper and nanotwin copper, and the second chip includes a second final wiring layer with a bonding wiring layer also featuring fine grain copper and nanotwin copper. The bonding interface between the chips comprises hybrid-bonded fine grain copper and nanotwin copper, enhancing bonding reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding structures are used, then manufacturing simplicity is maintained, but bonding reliability is insufficient

Engineering Contradiction:
Improvebonding reliabilityVSAvoidbonding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bonding electrode uses a composite structure combining fine grain copper (grain size 1 μm or less) and nanotwin copper, creating a multi-phase material system that leverages the high ductility of fine grain copper and the high strength of nanotwin copper to achieve superior bonding reliability

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The bonding electrode exhibits non-uniform microstructure with different regions having different properties: fine grain copper distributed throughout provides ductility and bonding capability, while nanotwin copper regions provide strength, creating local quality variations that optimize both bonding reliability and mechanical performance

Inventive Principle:
Principle #3Local quality

2Reliability

If copper grain size is reduced to fine grain level, then bonding reliability improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebonding reliabilityVSAvoidgrain size control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The invention specifies fine grain copper with grain size of 1 μm or less, representing a significant parameter change from conventional copper grain sizes. This parameter change enables enhanced bonding reliability through improved ductility and interfacial bonding capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

By combining fine grain copper with nanotwin copper, the invention creates a composite material system where the fine grain structure provides bonding reliability while the nanotwin structure contributes strength, allowing achievement of both reliability and manufacturability

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of fine grain copper and nanotwin copper in the bonding interface significantly increases the bonding reliability between the first and second semiconductor chips, leading to improved performance and stability of the semiconductor chip structure.

Implementation Method 1

The first bonding insulation layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid-bonded to the second bonding insulation layer and the second bonding electrode of the second bonding wiring layer

Methodology Applied
Scientific EffectHybrid bonding: Diffusion Welding

Data Source

PatentUS20250046740A1Semiconductor chip structure
Publication Date: 2025.02.06 SAMSUNG ELECTRONICS CO LTD
  • US20250046740A1 patent drawing
  • US20250046740A1 patent drawing
  • US20250046740A1 patent drawing

AI summary

A semiconductor chip structure includes a plurality of semiconductor chips. A bonding electrode included in each of the semiconductor chips is filled with nanotwin copper and fine grain copper is disposed in at least a portion of the bonding electrode.