Hybrid Core Substrate Architecture for High-Speed Signaling
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high-speed signaling and reliable interconnects due to increased complexity and thickness requirements, which lead to routing discontinuities and stress on metal planes, affecting performance and reliability.
Innovation Solution
The implementation of a hybrid core substrate architecture that combines a core substrate with an alternate substrate, enabling additional routing layers within the core thickness without increasing overall package thickness, and providing thermo-mechanical relief while maintaining reliability of first-level and second-level interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If substantially thick dielectrics and skip layers are incorporated to increase speeds and bandwidths, then high-speed signaling performance is improved, but routing complexity and metal plane discontinuities increase
Solution Approach 1:
The substrate is divided into a first substrate and a second substrate, each with their own metal layers and dielectric layers. This segmentation allows independent optimization of each substrate's routing structure, enabling high-speed signaling paths to be established without requiring complex skip layers or thick dielectrics that would increase overall routing complexity.
Solution Approach 2:
The patent transitions from a single-substrate vertical stacking approach to a multi-substrate lateral arrangement. By placing the first and second substrates adjacent to each other and establishing electrical connections between their respective metal layers, the patent creates additional routing dimensions that enable high-speed signaling without the need for complex vertical skip layers.
2Power
If additional layers and complex routing schemes are added to meet performance requirements, then bandwidth is improved, but lateral power delivery and non-high-speed signaling are degraded due to metal plane discontinuities
Solution Approach 1:
By segmenting the substrate into multiple independent substrates, each substrate can maintain its own continuous metal planes for power delivery. The first substrate can provide stable power planes for non-high-speed signaling, while the second substrate handles high-speed signaling paths, thus maintaining power delivery reliability while achieving high bandwidth.
Solution Approach 2:
The patent introduces an intermediary connection structure between the first and second substrates that enables high-bandwidth communication without disrupting the metal planes on either substrate. This intermediary approach allows power delivery networks to remain intact while still achieving the required bandwidth performance through the combined substrate architecture.
3Productivity
If routing layers are added within core thickness, then routing capability is improved, but overall package thickness increases
Solution Approach 1:
Instead of adding routing layers vertically within the core thickness, the patent utilizes the lateral dimension by placing multiple substrates adjacent to each other. This dimensional transition allows increased routing capability through additional substrate layers without increasing the overall package thickness, as the routing expansion occurs in the horizontal plane rather than the vertical plane.
Data Source
AI summary
Embodiments include a package substrate, a semiconductor package, and a method of forming the package substrate. A package substrate includes a core substrate between a first alternate core substrate and a second alternate core substrate. The first alternate core substrate includes conductive layers and vias. The package substrate includes a dielectric layer surrounding the core and first and second alternate substrates, a first conductive layer on a top surface of the dielectric layer, and a second conductive layer on top surfaces of the core and first and second alternate substrates, where the dielectric layer is over/under the core and first and second alternate substrates. The package substrate includes a third conductive layer on bottom surfaces of the core and first and second alternate substrates. The conductive layers are coupled to the vias within the first alternate core substrate, where the conductive layers and vias couple the second and third layers.