Hybrid Core Thread Partitioning for Parallel Instruction Scheduling

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Solution Overview

Problem

Computing devices with hybrid cores face inefficiencies in executing parallel instructions due to imbalanced workload execution across performance and efficient cores, as software services are unaware of the hardware configuration, leading to idle cores and suboptimal scheduling.

Innovation Solution

Dynamic partitioning of parallel threads into smaller sections based on core configuration and complexity, with streamed threading to support pipelining and data streaming from the OS level, allowing for efficient scheduling across hybrid cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software services execute parallel instructions on hybrid cores without awareness of hardware configuration, then implementation simplicity is maintained, but core utilization efficiency deteriorates leading to idle cores and suboptimal scheduling

Engineering Contradiction:
Improveimplementation simplicityVSAvoidcore utilization efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent introduces a scheduler as an intermediary component between software services and hybrid cores. The scheduler receives parallel instructions from software services, analyzes the hardware configuration of hybrid cores, and dynamically assigns instructions to appropriate cores. This mediator resolves the contradiction by maintaining implementation simplicity for software services while achieving optimal core utilization through intelligent scheduling.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The scheduler dynamically changes scheduling parameters based on hardware configuration detection. It detects the number and types of cores available, then adjusts instruction assignment strategies accordingly. This parameter adaptation enables the system to maintain simplicity while optimizing core utilization by matching instruction characteristics with appropriate core capabilities.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If parallel instructions are executed without dynamic partitioning, then scheduling complexity is reduced, but execution time increases due to imbalanced workload distribution

Engineering Contradiction:
Improvescheduling complexityVSAvoidexecution time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The scheduler dynamically partitions parallel instructions into smaller sub-tasks and distributes them across multiple cores. By segmenting the workload, the system achieves balanced execution without requiring complex manual scheduling. The automatic partitioning mechanism reduces execution time by utilizing all cores effectively while maintaining manageable scheduling complexity through algorithmic division of work.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scheduling system employs dynamic partitioning where instruction groups are divided and assigned based on real-time core availability and workload characteristics. This dynamic approach allows the system to adapt to changing conditions, balancing execution time optimization with scheduling complexity by making decisions at runtime rather than requiring static complex scheduling configurations.

Inventive Principle:
Principle #15Dynamics

3Use of energy by moving object

If static scheduling is used for parallel instructions, then scheduling overhead is minimized, but adaptability to hybrid core configurations deteriorates causing idle cores

Engineering Contradiction:
Improvescheduling overheadVSAvoidadaptability to hybrid core configuration
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The scheduler performs preliminary detection of hybrid core configuration before executing parallel instructions. By detecting the number and types of cores in advance, the scheduler can pre-plan optimal instruction distribution. This preliminary action reduces scheduling overhead by avoiding runtime reconfiguration while maintaining high adaptability through configuration-aware scheduling strategies.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the scheduler continuously monitors core execution status and adjusts instruction assignment accordingly. This feedback loop enables the system to maintain low overhead by using simple status checks while achieving high adaptability to hybrid core configurations through dynamic response to monitored performance data, preventing idle cores by reallocating work based on actual core availability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20230168898A1Methods and apparatus to schedule parallel instructions using hybrid cores
Publication Date: 2023.06.01 INTEL CORP
  • US20230168898A1 patent drawing
  • US20230168898A1 patent drawing
  • US20230168898A1 patent drawing

AI summary

Methods, apparatus, systems, and articles of manufacture to schedule parallel instructions using hybrid cores are disclosed. An example apparatus includes thread processing circuitry to split a first thread of the parallel threads into partitions; scheduling circuitry to: select (a) a first core to execute a first partition of the partitions and (b) a second core different than the first core to execute a second partition of the partitions; and generate an execution schedule based on the selection, the interface circuitry to transmit the execution schedule to a device that schedules instructions on the first and second core.