Hybrid Counter Circuit for Arbitrary Value Increment
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Solution Overview
Problem
Traditional counter circuits require complex logic to manage carry bits during addition operations, limiting their efficiency and flexibility, especially when only a relative count change is necessary, and Galois counters can only be incremented one step at a time, restricting their usage.
Innovation Solution
A hybrid counter system comprising first counter control circuitry for maintaining a binary value and second counter control circuitry for a bit sequence with N discrete states, where the second counter transitions based on a carry out signal from the first counter, allowing arbitrary value increments without managing carry bits across all bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a traditional binary counter with adder circuitry is used to allow arbitrary value increments, then the counter can be incremented by arbitrary values, but the device complexity increases due to carry bit management logic
Solution Approach 1:
The counter is divided into two separate counters: a first counter that handles arbitrary value increments with full adder circuitry, and a second counter that only increments by one in response to a carry-out signal. This segmentation allows each counter to be optimized for its specific function, reducing overall complexity while maintaining arbitrary increment capability.
Solution Approach 2:
Instead of implementing full adder circuitry for all counter bits, the patent applies adder circuitry only to the most significant bits (first counter), while the less significant bits (second counter) use simpler increment-by-one logic triggered by carry-out. This partial application of complex circuitry reduces overall device complexity while preserving arbitrary increment functionality where it matters most.
2Device complexity
If a Galois counter is used to reduce hardware overhead, then the hardware requirements are reduced, but the counter can only be incremented one step at a time
Solution Approach 1:
The patent combines a Galois counter (second counter) with a traditional binary counter (first counter) into a hybrid counter system. The Galois counter provides hardware efficiency for the lower bits, while the binary counter with adder circuitry provides arbitrary increment capability for the upper bits. The carry-out signal from the binary counter triggers the Galois counter, merging the advantages of both approaches.
Solution Approach 2:
Different parts of the counter use different architectures optimized for their specific requirements: the most significant bits use binary counter with adder circuitry for flexible arbitrary increments, while the least significant bits use Galois counter for hardware efficiency. This local differentiation allows each part to have the quality needed for its function.
Data Source
AI summary
An apparatus and method are provided for maintaining a counter value. The apparatus has first counter control circuitry for maintaining a first counter value representing a first portion of a hybrid counter value, and second counter control circuitry for maintaining a second counter value representing a second portion of the hybrid counter value, wherein the second portion is a higher order portion of the hybrid counter value than the first portion. The first counter control circuitry is arranged to maintain the first counter value as a binary value that indicates a magnitude of the first counter value, the first counter control circuitry comprising adder circuitry that is responsive to an adjustment value to update the first counter value by performing an addition operation to add the adjustment value to a current binary value of the first counter value, and to generate a carry out signal which is set when a carry out is generated by the addition operation. The second counter control circuitry is arranged to maintain the second counter value as a bit sequence having N discrete states, and is responsive to the carry out signal being set to transition the second counter value from the current discrete state to a new discrete state. This allows an arbitrary value to be used as the adjustment value, that is smaller than or equal to the maximum value of the first counter, whilst avoiding the need for the generation and handling of carry bits to be managed across the entire bit range of the hybrid counter value.